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TLK6002 Datasheet(PDF) 13 Page - Texas Instruments |
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TLK6002 Datasheet(HTML) 13 Page - Texas Instruments |
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13 / 96 page  TLK6002 www.ti.com SLLSE34 – MAY 2010 Table 2-1. Pin Description – Signal Pins (continued) Terminal Direction Type Description Signal BGA Supply Input JTAG Input Data. TDI is used to serially shift test data and test instructions into the device during the operation of LVCMOS the test port. In system applications where JTAG is not implemented, this input signal may be left floating. 1.5V/1.8V During pin based power down (PD_TRXA_N and PD_TRXB_N asserted low), this pin is not pulled up. During TDI R15 VDDO2 register based power down (1.15 asserted high both channels), this pin is pulled up normally. (Internal Pullup) JTAG Output Data. TDO is used to serially shift test data and test instructions out of the device during operation of Output the test port. When the JTAG port is not in use, TDO is in a high impedance state. LVCMOS TDO R14 1.5V/1.8V During device reset (RESET_N asserted low) this pin is floating. During pin based power down (PD_TRXA_N and VDDO2 50 Ω PD_TRXB_N asserted low), this pin is floating. During register based power down (1.15 asserted high both Driver channels), this pin is floating. Input JTAG Mode Select. TMS is used to control the state of the internal test-port controller. In system applications LVCMOS where JTAG is not implemented, this input signal can be left unconnected. 1.5V/1.8V During pin based power down (PD_TRXA_N and PD_TRXB_N asserted low), this pin is not pulled up. During TMS R3 VDDO3 register based power down (1.15 asserted high both channels), this pin is pulled up normally. (Internal Pullup) Input JTAG Clock. TCK is used to clock state information and test data into and out of the device during boundary scan LVCMOS operation. In system applications where JTAG is not implemented, this input signal should be grounded. TCK T16 w/Hysteresi s 1.5V/1.8V VDDO2 Input JTAG Test Reset. TRST_N is used to reset the JTAG logic into system operational mode. This input can be left LVCMOS unconnected in the application and is pulled down internally, disabling the JTAG circuitry. If JTAG is implemented 1.5V/1.8V on the application board, this signal should be deasserted (high) during JTAG system testing, and otherwise TRST_N T3 VDDO3 asserted (low) during normal operation mode. (Internal During pin based power down (PD_TRXA_N and PD_TRXB_N asserted low), this pin is not pulled down. During Pulldown) register based power down (1.15 asserted high both channels), this pin is pulled down normally. Input Test Enable. This signal is used during the device manufacturing process. It should be grounded through a resistor LVCMOS in the device application board. The application board should allow the flexibility of easily reworking this signal to a TESTEN T17 1.5V/1.8V high level if device debug is necessary (by including an uninstalled resistor to VDDO2). VDDO2 Input General Purpose Input Zero. This signal is used during the device manufacturing process. It should be grounded LVCMOS through a resistor on the device application board. The application board should also allow the flexibility of easily GPI0 R4 1.5V/1.8V reworking this signal to a high level if device debug is necessary (by including an uninstalled resistor to VDDO3). VDDO3 Input General Purpose Input One. This signal can be used to logically combine an external status condition with LOSA LVCMOS or LOSB if enabled in an mdio register. Note that if GPI1 is low, LOSA/B will be asserted if logical combination is GPI1 K10 1.5V/1.8V enabled. Similarly, if GPI1 is high, LOSA/B will be deasserted. If unused, this input should be grounded in the VDDO1 device application (not floating). SERDES Channel A Analog Testability I/O. This signal is used during the device manufacturing process. It should AMUXA U5 Analog I/O be left unconnected in the device application. SERDES Channel B Analog Testability I/O. This signal is used during the device manufacturing process. It should AMUXB V14 Analog I/O be left unconnected in the device application. RESRA, K8 HSTL Impedance Matching Resistors. These resistors are used as a reference for internal terminations on the RESTA, M1 Analog HSTL inputs and outputs. Each RES* pin requires it’s own resistor, sharing resistors between RES* pins is not RESRB, J14 Input possible. A 50 ohm 0.5% tolerance resistor should be selected to guarantee device datasheet specified parallel RESTB M18 interface timing specification. Copyright © 2010, Texas Instruments Incorporated Description 13 Submit Documentation Feedback Product Folder Link(s): TLK6002 |
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