TLK6002 datasheet(10/96 Pages) TI

10 / 96 page

TLK6002

SLLSE34 – MAY 2010

www.ti.com

Table 2-1. Pin Description – Signal Pins (continued)

Terminal

Direction

Type

Description

Signal

BGA

Supply

Parallel Input Channel B Transmit Data Bus.

J17

These data signals are synchronous to and sampled by TXCLK_B.

H17

J16

Two data modes are supported, SDR (Single Data Rate), and DDR (Double Data Rate). SDR has two valid symbols

H18

per TXCLK_B cycle, and DDR has four valid symbols per TXCLK_B cycle.

K15

When input data is in 8b/10b encoded format (a.k.a. 20-bit data mode), TDB_[19:10] and TDB_[9:0] each carry a

K16

symbol.

L14

L16

When input data is encoded internal to TLK6002 (8b/10b encoder enabled, a.k.a. 16-bit data mode), two symbols

M14

Input HSTL

are input at a time, defined as follows:

M16

TDB_[19:0]

1.5V/1.8V

M15

One Symbol – TDB_[8] contains the control bit (k-character indication) of data byte TDB_[7:0], and TDB_[9] is

VDDQB

P17

unused and should be grounded.

N14

Other Symbol – TDB_[18] contains the control bit (k-character indication) of data byte TDB_[17:10], and TDB_[19] is

N16

unused and should be grounded.

J18

M17

Unused parallel input pins must be grounded.

R17

See the following figures for more detail:

P15

Figure 2-1 20-bit SDR Parallel Interface Mode

P14

Figure 2-2 16-bit SDR Parallel Interface Mode

P18

Figure 2-3 20-bit DDR Parallel Interface Mode

Parallel Channel B Receive Data Bus.These output receive data signals are synchronous to RXCLK_B.

Two data modes are supported, SDR (Single Data Rate), and DDR (Double Data Rate). SDR has two valid symbols

D18

per RXCLK_B cycle, and DDR has four valid symbols per RXCLK_B cycle.

E17

B18

When output data is in 8b/10b encoded format (a.k.a. 20-bit data mode), RDB_[19:10] and RDB_[9:0] each carry a

C17

symbol.

F16

When output data is decoded internal to TLK6002 (8b/10b decoder enabled, a.k.a. 16-bit data mode), two symbols

F17

are output at a time, defined as follows:

A17

B16

One Symbol - RDB_[8] contains the control bit (k-character indication) of data byte RDB_[7:0], and RDB_[9]

C16

Output

indicates whether a 8b/10b disparity error was detected or an invalid code was received coincident with that

D16

HSTL

particular symbol

RDB_[19:0]

C18

1.5V/1.8V

Other Symbol - RDB_[18] contains the control bit (k-character indication) of data byte RDB_[17:10], and RDB_[19]

F15

VDDQB

indicates whether a 8b/10b disparity error was detected or an invalid code was received coincident with that

A16

particular symbol.

B15

D15

During device reset (RESET_N asserted low) these pins are driven low. During pin based power down

E15

(PD_TRXB_N asserted low), these pins are floating. During register based power down (1.15 asserted high), these

G16

pins are floating.

H15

See the following figures for more detail:

G15

Figure 2-1 20-bit SDR Parallel Interface Mode

G14

Figure 2-2 16-bit SDR Parallel Interface Mode

Figure 2-3 20-bit DDR Parallel Interface Mode

Receive Output Channel B Clock. RXCLK_B is synchronous to RDB_[19:0], and may be used externally to

sample Channel B output parallel data.

Output

In SDR mode, this signal is equal in frequency to serial bit rate / 20.

HSTL

RXCLK_B

F18

In DDR mode, this signal is equal in frequency to serial bit rate / 40.

1.5V/1.8V

VDDQB

During device reset (RESET_N asserted low) this pin is driven low.

During pin based power down (PD_TRXB_N asserted low), this pin is floating.

During register based power down (1.15 asserted high), these pins are floating.

Receive PRBS Channel B Error Free (Pass) Indicator

When PRBS test is enabled (PRBS_EN=1):

PRBSB_PASS=1 indicates that PRBS pattern reception is error free.

Output

PRBSB_PASS=0 indicates that a PRBS error is detected.

LVCMOS

PRBSB_PASS

V18

1.5V/1.8V

During device reset (RESET_N asserted low) this pin is driven low.

VDDO2 40

Ω During pin based power down (PD_TRXB_N asserted low), this pin is floating.

Driver

During register based power down (1.15 asserted high), this pin is floating.

It is highly recommended that PRBSB_PASS be brought to easily accessible point on the application board

(header), in the event that debug is required.

Input

Encoder/Decoder Channel B Enable: When this pin is asserted high, the internal 8b/10b encoder/decoder is

LVCMOS

enabled. This signal is OR’d with MDIO register bits, and should be tied low if software control is desired.

CODEB_EN

V16

1.5V/1.8V

VDDO2

Description

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