7549 datasheet(71/86 Pages) RENESAS

71 / 86 page

Rev.2.02

Mar 31, 2009

Page 69 of 81

REJ03B0202-0202

7549 Group

(6) Timing Requirements

Table 20 Timing requirements (1)

(VCC = 4.0 to 5.5 V, VSS = 0 V, Ta =

−20 to 85 °C, unless otherwise noted)

NOTES:

1. As for CAP0, it is the value when noise filter is not used.

2. In this time, bit 6 of the serial I/O control register (address 001A16) is set to “1” (clock synchronous serial I/O is selected).

When bit 6 of the serial I/O control register is “0” (clock asynchronous serial I/O is selected), the rating values are divided by 4.

Table 21 Timing requirements (2)

(VCC = 2.4 to 5.5 V, VSS = 0 V, Ta =

−20 to 85 °C, unless otherwise noted)

NOTES:

1. As for CAP0, it is the value when noise filter is not used.

2. In this time, bit 6 of the serial I/O control register (address 001A16) is set to “1” (clock synchronous serial I/O is selected).

When bit 6 of the serial I/O control register is “0” (clock asynchronous serial I/O is selected), the rating values are divided by 4.

Reset input “L” pulse width

External clock input cycle time

External clock input “H” pulse width

External clock input “L” pulse width

INT0, INT1, CAP0 input “H” pulse width (Note 1)

INT0, INT1, CAP0 input “L” pulse width (Note 1)

Serial I/O clock input cycle time (Note 2)

Serial I/O clock input “H” pulse width (Note 2)

Serial I/O clock input “L” pulse width (Note 2)

Serial I/O input set up time

Serial I/O input hold time

Symbol

Parameter

Limits

Unit

Min.

125

800

370

220

100

Typ.

µs

Max.

______

tW(RESET)

tC(XIN)

tWH(XIN)

tWL(XIN)

tWH(INT0)

tWL(INT0)

tC(SCLK)

tWH(SCLK)

tWL(SCLK)

tsu(RXD-SCLK)

th(SCLK-RXD)