7549 datasheet(82/86 Pages) RENESAS

82 / 86 page

Rev.2.02

Mar 31, 2009

Page 80 of 81

REJ03B0202-0202

7549 Group

Notes on Watchdog Timer

1. Watchdog Timer Underflow

The watchdog timer operates in wait mode. To prevent

underflow, write to the watchdog timer control register.

The watchdog timer stops in stop mode, but starts counting at the

same time as exiting stop mode. After exiting stop mode, it

continues counting during oscillation stabilization time. To

prevent underflow during the period, the watchdog timer H count

source selection bit (bit 7) in the watchdog timer control register

(address 003916) should be set to “0” before executing the STP

instruction.

Note that the watchdog timer continues counting even if the STP

instruction is executed in the following two conditions:

1 Stopping the low-speed on-chip oscillator: Disabled (bit 4 in

FSROM2)

Source clock of the watchdog timer: Low-speed on-chip

oscillator/16 (bit 0 in FSROM2)

2 Stopping the low-speed on-chip oscillator: Disabled (bit 4 in

FSROM2)

Source clock of the watchdog timer:

φSOURCE (bit 0 in

FSROM2)

φSOURCE: Low-speed on-chip oscillator (bits 5 and 4 in

CLKM)

2. STP instruction function selection bit

The function of the STP instruction can be selected by the bit 2 in

FSROM2. This bit cannot be used for rewriting by executing the

STP instruction.

• When this bit is set to “0”, stop mode is entered by executing

the STP instruction.

• When this bit is set to “1”, internal reset occurs by executing

the STP instruction.

Notes on RESET pin

1. Connecting capacitor

In case where the RESET signal rise time is long, connect a

ceramic capacitor or others across the RESET pin and VSS pin.

And use a 1000 pF or more capacitor for high frequency use.

When connecting the capacitor, note the following:

• Make the length of the wiring which is connected to a

capacitor as short as possible.

• Be sure to verify the operation of application products on the

user side.

If the several nanosecond or several ten nanosecond impulse

noise enters the RESET pin, it may cause a microcomputer

failure.

Note on Generating Clock Circuit

1. Switching to XIN/XCIN Oscillator

After a reset is cleared, operation starts using the low-speed on-

chip oscillator. When switching to XIN/XCIN oscillator, make

sure to set a sufficient wait duration with the on-chip oscillator to

allow the XIN/XCIN oscillator to stabilize.

Note on Oscillation Control

For use with the oscillation stabilization set bit after release of

the STP instruction set to “1”, set values in timer 1 and prescaler

12 after fully appreciating the oscillation stabilization time of the

oscillator to be used.

Notes on Oscillation Stop Detection Circuit

(1) Do not execute the transition to “state 2’a” shown in Figure

68 State transition of oscillation stop detection circuit. In

this state, no reset is triggered and the MCU is stopped even

when the XIN oscillation stops.

(2) After an oscillation stop detection reset, if this reset is

enabled while bits XIN oscillation stop detection function

active and oscillation stop detection status are retained, a

reset is triggered again.

(3) The oscillation stop detection status bit is initialized under

the following conditions:

• External reset, power-on reset, low-voltage detection reset,

watchdog timer reset, and reset by the STP instruction

function.

• Write 0 to the XIN oscillation stop detection function active

bit

(4) While the oscillation stop detection function is in active, the

oscillation stop detection status bit may set to 1 when the

watchdog timer underflows or by a reset when the STP

instruction is executed with the STP instruction function

selection bit set to 1.

When an oscillation stop detection reset is triggered,

reconfirm that oscillation is stopped.

(5) The oscillation stop detection circuit is not included in the

emulator MCU “M37549RLSS”.

Note on Power Source Voltage

When the power source voltage value of a microcomputer is less

than the value which is indicated as the recommended operating

conditions, the microcomputer does not operate normally and

may perform unstable operation.

In a system where the power source voltage drops slowly when

the power source voltage drops or the power supply is turned off,

reset a microcomputer when the supply voltage is less than the

recommended operating conditions and design a system not to

cause errors to the system by this unstable operation.

Note on Handling of Power Source Pin

In order to avoid a latch-up occurrence, connect a capacitor

suitable for high frequencies as bypass capacitor between power

source pin (VCC pin) and GND pin (VSS pin). A ceramic

capacitor of 0.01

µF to 0.1 µF is recommended.

Connect a capacitor across the power source pin and GND pin

with the shortest possible wiring.

7549 Datasheet(PDF) 82 Page - Renesas Technology Corp

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