7549 datasheet(79/86 Pages) RENESAS

79 / 86 page

Rev.2.02

Mar 31, 2009

Page 77 of 81

REJ03B0202-0202

7549 Group

Notes on Interrupts

1. Change of relevant register settings

When not requiring for the interrupt occurrence synchronous

with the following case, take the sequence shown in Figure 5.

• When switching external interrupt active edge

• When switching interrupt sources of an interrupt vector

address where two or more interrupt sources are allocated

Fig 89. Sequence of changing relevant register

When setting the followings, the interrupt request bit of the

corresponding interrupt may be set to “1”.

• When switching external interrupt active edge

INT0 interrupt edge selection bit

(bit 0 of Interrupt edge selection register (address 003A16))

INT1 interrupt edge selection bit

(bit 1 of Interrupt edge selection register)

Capture 0 interrupt edge selection bit

(bits 1 and 0 of capture mode register (address 3216))

Capture 1 interrupt edge selection bit

(bits 3 and 2 of capture mode register)

2. Check of interrupt request bit

When executing the BBC or BBS instruction to determine an

interrupt request bit immediately after this bit is set to “0”, take

the following sequence.

If the BBC or BBS instruction is executed immediately after an

interrupt request bit is cleared to “0”, the value of the interrupt

request bit before being cleared to “0” is read.

Fig 90. Sequence of check of interrupt request bit

Notes on Timers

1. Division Ratio of Timers 1, 2, and A

When n (0 to 255) is written to a timer latch, the frequency

division ratio is 1/(n

+1).

2. Switching Count Source of Timers 1, 2, and A

When a count source of timer 1, timer 2 or timer A is switched,

stop a count of the timer.

3. Reading from and Writing to Timers 1, 2, and

Prescaler 12

If the timer/prescaler count source clock and

φSOURCE are

different clocks, the timers and prescaler cannot be read or

written. Select the same clock to enable read and write

operations.

Note that timer 2 can be read and written even using a

different clock while its counting is stopped.

1Prescaler 12 and timer 1 cannot be read/written in the

following conditions:

Prescaler 12 count source: XCIN input clock

φSOURCE: Clock other than XCIN input clock

2Timer 2 cannot be read/written during counting in the

following conditions:

Timer 2 count source: Prescaler 12

Prescaler 12 count source: XCIN input clock

φSOURCE: Clock other than XCIN input clock

Timer 2 count source: Timer A underflow

Timer A count source: XCIN input clock

φSOURCE: Clock other than XCIN input clock

Timer 2 count source: Timer A underflow

Timer A count source: low-speed on-chip oscillator output

φSOURCE: Clock other than low-speed on-chip oscillator

4. Count Source of Prescaler 12

The XCIN input clock can be selected as the prescaler count

source only if the 32 kHz quartz crystal oscillator is selected by

the oscillation method selection bit in FSROM1.

5. Timer Value Setting

When the timer A write control bit is set to “write to only latch”,

written data is written to only to the latch even when the timer is

stopped. To set the initial setting value when the timer is stopped,

select “Write to timer and latch simultaneously” beforehand.

Set the interrupt edge selection bit active edge

switch bit, or the interrupt source selection bit.

NOP (One or more instructions)

Set the corresponding interrupt enable bit to

“0” (disabled).

Set the corresponding interrupt request bit to “0”

(no interrupt request).

Set the corresponding interrupt enable bit to “1”

(enabled).

NOP (one or more instructions)

Set the interrupt request bit to “0” (no interrupt issued)

Execute the BBC or BBS instruction

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