7549 datasheet(22/86 Pages) RENESAS

22 / 86 page

Rev.2.02

Mar 31, 2009

Page 20 of 81

REJ03B0202-0202

7549 Group

Interrupts

The 7549 group interrupts are vector interrupts with a fixed

priority scheme, and generated by 12 sources: 4 external, 7

internal, and 1 software.

The interrupt sources, vector addresses(1), and interrupt priority

are shown in Table 8.

Each interrupt except the BRK instruction interrupt has the

interrupt request bit and the interrupt enable bit. These bits and

the interrupt disable flag (I flag) control the acceptance of

interrupt requests. Figure 18 shows an interrupt control diagram.

An interrupt requests is accepted when all of the following

conditions are satisfied:

• Interrupt disable flag.................................“0”

• Interrupt request bit...................................“1”

• Interrupt enable bit....................................“1”

Though the interrupt priority is determined by hardware, priority

processing can be performed by software using the above bits

and flag.

Table 8

Interrupt vector address and priority

NOTES:

1. Vector addressed contain internal jump destination addresses.

2. Reset function in the same way as an interrupt with the highest priority.

Interrupt source

Priority

Vector addresses

(Note 1)

Interrupt request generating conditions

Remarks

High-

order

Low-

order

Reset (Note 2)

FFFD16

FFFC16

At reset input

Non-maskable

Serial I/O receive

FFFB16

FFFA16

At completion of serial I/O data receive

Valid only when serial I/O is selected

Serial I/O transmit

FFF916

FFF816

At completion of serial I/O transmit shift or

when transmit buffer is empty

Valid only when serial I/O is selected

INT0

4FFF716

FFF616

At detection of either rising or falling edge

of INT0 input

External interrupt

(active edge selectable)

INT1

5FFF516

FFF416

At detection of either rising or falling edge

of INT1 input

External interrupt

(active edge selectable)

Key-on wakeup

FFF316

FFF216

At falling of conjunction of input logical

level for port P1 (at input)

External interrupt (valid at falling edge)

Capture

FFF116

FFF016

At detection of either rising or falling edge

of Capture 0 input

External interrupt

(active edge selectable)

Compare

FFEF16

FFEE16

At compare matched

Compare interrupt source is selected.

Timer A

FFED16

FFEC16

At timer A underflow

Timer 210

FFEB16

FFEA16

At timer 2 underflow

A/D conversion

FFE916

FFE816

At completion of A/D conversion

Timer 112

FFE716

FFE616

At timer 1 underflow

STP release timer underflow

Not used

FFE516

FFE416

FFE316

FFE216

FFE116

FFE016

FFDF16

FFDE16

BRK instruction

FFDD16

FFDC16

At BRK instruction execution

Non-maskable software interrupt

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