MAX9268GCMSLASHV+T datasheet(19/35 Pages) MAXIM

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Gigabit Multimedia Serial Link Deserializer

with LVDS System Interface

______________________________________________________________________________________ 19

synchronous with TXCLKOUT_. The MAX9268 deserial-

izer decodes the audio stream and stores audio words

in a FIFO. Audio rate detection uses an internal oscillator

to continuously determine the audio data rate and output

the audio in I2S format. The audio channel is enabled by

default. When the audio channel is disabled, the audio

data input (SD) on the serializer becomes a control input

(CNTL0) and SD/CNTL0 becomes a control output on

the deserializer.

Low TXCLKOUT_ frequencies limit the maximum

audio sampling rate. Table 4 lists the maximum audio

sampling rate for various TXCLKOUT_ frequencies.

Spread-spectrum settings do not affect the I2S data rate

or WS clock frequency.

Additional MCLK Output for

Audio Applications

Some audio DACs such as the MAX9850 do not require

a synchronous main clock (MCLK), while other DACs

require MCLK to be a specific multiple of WS. If the audio

DAC chip needs the MCLK to be a multiple of WS, use

an external PLL to regenerate the required MCLK from

WS or SCK.

For audio applications that have WS synchronous to

TXCLKOUT_, the MAX9268 provides a divided clock

output on CNTL2/MCLK at the expense of one less

control line in 4-channel mode (3-channel mode is not

affected). By default, CNTL2/MCLK operates as a con-

trol data output, and MCLK is turned off. Set MCLKDIV

(MAX9268 register 0x12, D[6:0]) to a nonzero value

to enable the MCLK output. Set MCLKDIV to 0x00 to

disable MCLK and set CNTL2/MCLK as a control data

output.

The output MCLK frequency is:

SRC

MCLK

MCLKDIV

where:

fSRC = the MCLK source frequency (Table 5)

MCLKDIV = the divider ratio from 1 to 127

Choose MCLKDIV values such that fMCLK is not

greater than 60MHz. MCLK frequencies derived from

TXCLKOUT_ (MSCLKSRC = 0) are not affected by

spread-spectrum settings in the MAX9268. However,

enabling spread spectrum in the GMSL serializer intro-

duces spread spectrum into MCLK. Spread-spectrum

settings of either device do not affect MCLK frequencies

derived from the internal oscillator. The internal oscilla-

tor frequency ranges from 100MHz to 150MHz over all

process corners and operating conditions.

Table 4. Maximum Audio WS Frequency (kHz) for Various TXCLKOUT_ Frequencies

Table 5. fSRC Settings

WORD

LENGTH

(BITS)

TXCLKOUT_ FREQUENCY

(DRS = LOW)

(MHz)

TXCLKOUT_ FREQUENCY

(DRS = HIGH)

(MHz)

12.5

16.6

> 20

6.25

7.5

8.33

> 10

> 192

185.5

> 192

185.5

> 192

174.6

> 192

174.6

> 192

152.2

182.7

> 192

152.2

182.7

> 192

123.7

148.4

164.3

> 192

123.7

148.4

164.3

> 192

MCLKSRC SETTING

(REGISTER 0x12, D7)

DATA-RATE SETTING

BUS-WIDTH SETTING

MCLK SOURCE FREQUENCY (fSRC)

High speed

3-channel mode

3 x fTXCLKOUT_

4-channel mode

4 x fTXCLKOUT_

Low speed

3-channel mode

6 x fTXCLKOUT_

4-channel mode

8 x fTXCLKOUT_

—

Internal oscillator

(120MHz, typ)

MAX9268GCM/V+T Datasheet(PDF) 19 Page - Maxim Integrated Products

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