MAX9268GCMSLASHV+T datasheet(20/35 Pages) MAXIM

20 / 35 page

Gigabit Multimedia Serial Link Deserializer

with LVDS System Interface

20 _____________________________________________________________________________________

Control Channel and Register Programming

The control channel is available for the FC to send and

receive control data over the serial link simultaneously with

the high-speed data, to program registers on the link serial-

izer/deserializer or to program peripherals. Configuring the

CDS pin allows a FC to control the link from the side of the

serializer or deserializer, or with dual FCs from both sides,

to support a wide variety of applications.

The control channel runs in base mode or bypass mode

according to the mode-selection (MS) input of the device

connected to the FC. In base mode, the control-channel

transactions are half-duplex and in bypass mode they are

full-duplex.

Base Mode

In base mode the FC is the host, and in order to access the

registers of the serializer or deserializer it must use the

GMSL UART format and protocol. The FC accesses

peripherals with an I2C interface by sending GMSL UART

packets, which are converted to I2C by the serializer

or deserializer on the remote side of the link. The FC

communicates with a UART peripheral in base mode

(through INTTYPE register settings) using the GMSL UART

protocol. The device addresses of the GMSL serializer and

MAX9268 in base mode are programmable. The default

MAX9268 device address is determined by ADD0 and

ADD1 upon power-up, or after returning from a power-

down state (Table 2).

When the peripheral interface uses I2C (default), the GMSL

serializer/MAX9268 convert packets to I2C that have device

addresses different from those of the GMSL serializer or

MAX9268. The converted I2C bit rate is the same as the

original UART bit rate.

The GMSL serializer embeds control signals going to the

MAX9268 in the high-speed forward link. The MAX9268

uses a proprietary differential line coding to send signals

back towards the serializer. The speed of the control chan-

nel ranges from 100kbps to 1Mbps in both directions. The

GMSL serializer and MAX9268 deserializer automatically

detect the control-channel bit rate in base mode. Packet bit

rates can vary up to 3.5x from the previous bit rate (see the

Changing the Clock Frequency section). Figure 16 shows

the UART protocol for writing and reading in base mode

between the FC and the GMSL serializer/MAX9268.

Figure 17 shows the UART data format. Figures 18 and 19

detail the formats of the SYNC byte (0x79) and the ACK

byte (0xC3). The FC and the connected slave chip gen-

erate the SYNC byte and ACK byte, respectively. Events

such as device wake-up and interrupt generate transitions

on the control channel that should be ignored by the FC.

Data written to the GMSL serializer/MAX9268 registers do

not take effect until after the acknowledge byte is sent.

This allows the FC to verify write commands received with-

out error, even if the result of the write command directly

affects the serial link. The slave uses the SYNC byte to

synchronize with the host UART data rate automatically. If

the INT or MS inputs of the MAX9268 toggle while there is

control-channel communication, the control-channel com-

munication can be corrupted since INT has priority on the

control channel. In the event of a missed acknowledge, the

C should assume there was an error in the packet when

the slave device receives it, or that an error occurred during

the response from the slave device. In base mode, the FC

must keep the UART Tx/Rx lines high for 16 bit times before

sending a new packet.

As shown in Figure 20, the remote-side device converts

the packets going to or coming from the peripherals from

the UART format to the I2C format and vice versa. The

remote device removes the byte number count and adds or

receives the ACK between the data bytes of I2C. The I2C’s

data rate is the same as the UART data rate.

Figure 16. GMSL UART Protocol for Base Mode

WRITE DATA FORMAT

SYNC

DEV ADDR + R/W

REG ADDR

NUMBER OF BYTES

SYNC

DEV ADDR + R/W

REG ADDR

NUMBER OF BYTES

BYTE 1

BYTE N

ACK

BYTE N

BYTE 1

ACK

MASTER READS FROM SLAVE

READ DATA FRMAT

MASTER WRITES TO SLAVE

MASTER READS FROM SLAVE

MAX9268GCM/V+T Datasheet(PDF) 20 Page - Maxim Integrated Products

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