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WM8750CLSEFL/R Datasheet(PDF) 44 Page - Wolfson Microelectronics plc |
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WM8750CLSEFL/R Datasheet(HTML) 44 Page - Wolfson Microelectronics plc |
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44 / 65 page ![]() WM8750L Production Data w PD, Rev 4.4, August 2012 44 AUDIO INTERFACE CONTROL The register bits controlling audio format, word length and master / slave mode are summarised in Table 34. MS selects audio interface operation in master or slave mode. In Master mode BCLK, ADCLRC and DACLRC are outputs. The frequency of ADCLRC and DACLRC is set by the sample rate control bits SR[4:0] and USB. In Slave mode BCLK, ADCLRC and DACLRC are inputs. REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R7 (07h) Digital Audio Interface Format 7 BCLKINV 0 BCLK invert bit (for master and slave modes) 0 = BCLK not inverted 1 = BCLK inverted 6 MS 0 Master / Slave Mode Control 1 = Enable Master Mode 0 = Enable Slave Mode 5 LRSWAP 0 Left/Right channel swap 1 = swap left and right DAC data in audio interface 0 = output left and right data as normal 4 LRP 0 right, left and i2s modes – LRCLK polarity 1 = invert LRCLK polarity 0 = normal LRCLK polarity DSP Mode – mode A/B select 1 = MSB is available on 1st BCLK rising edge after LRC rising edge (mode B) 0 = MSB is available on 2nd BCLK rising edge after LRC rising edge (mode A) 3:2 WL[1:0] 10 Audio Data Word Length 11 = 32 bits (see Note) 10 = 24 bits 01 = 20 bits 00 = 16 bits 1:0 FORMAT[1:0] 10 Audio Data Format Select 11 = DSP Mode 10 = I 2S Format 01 = Left justified 00 = Right justified Table 34 Audio Data Format Control Notes: 1. The BCLK invert function (BCLKINV) is not supported by the ADC output in Master or Slave modes. Inverted BCLK operation (BCLKINV=1) is only supported for DAC-only modes. 2. In Right-Justified mode, 32-bit word length is not supported 3. In Right Justified mode, 16-bit and 20-bit word length is only supported if DCVDD ≤ 1.5V |
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