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WM8750CLSEFL/R Datasheet(PDF) 21 Page - Wolfson Microelectronics plc

Part # WM8750CLSEFL/R
Description  Stereo CODEC for Portable Audio Applications
PDF  65 Pages
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Manufacturer  WOLFSON [Wolfson Microelectronics plc]
Direct Link  http://www.wolfsonmicro.com
Logo WOLFSON - Wolfson Microelectronics plc

WM8750CLSEFL/R Datasheet(HTML) 21 Page - Wolfson Microelectronics plc

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Production Data
WM8750L
w
PD, Rev 4.4, August 2012
21
The internal MICBIAS circuitry is shown below. Note that the is a maximum source current capability
for MICBIAS is 3mA. The external biasing resistors therefore must be large enough to limit the
MICBIAS current to 3mA.
AGND
MICBIAS
= 1.8 x VMID
= 0.9 X AVDD
VMID
internal
resistor
internal
resistor
MICB
Figure 8 Microphone Bias Schematic
PGA CONTROL
The PGA matches the input signal level to the ADC input range. The PGA gain is logarithmically
adjustable from +30dB to –17.25dB in 0.75dB steps. Each PGA can be controlled either by the user
or by the ALC function (see Automatic Level Control). When ALC is enabled for one or both channels,
then writing to the corresponding PGA control register has no effect.
The gain is independently adjustable on both Right and Left Line Inputs. Additionally, by controlling
the register bits LIVU and RIVU, the left and right gain settings can be simultaneously updated.
Setting the LIZC and RIZC bits enables a zero-cross detector which ensures that PGA gain changes
only occur when the signal is at zero, eliminating any zipper noise. If zero cross is enabled a timeout
is also available to update the gain if a zero cross does not occur. This function may be enabled by
setting TOEN in register R23 (17h).
The inputs can also be muted in the analogue domain under software control. The software control
registers are shown in Table 9. If zero crossing is enabled, it is necessary to enable zero cross
timeout to un-mute the input PGAs. This is because their outputs will not cross zero when muted.
Alternatively, zero cross can be disabled before sending the un-mute command.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R0 (00h)
Left Channel
PGA
8
LIVU
0
Left Volume Update
0 = Store LINVOL in intermediate
latch (no gain change)
1 = Update left and right channel
gains (left = LINVOL, right =
intermediate latch)
7
LINMUTE
1
Left Channel Input Analogue Mute
1 = Enable Mute
0 = Disable Mute
Note: LIVU must be set to un-mute.
6
LIZC
0
Left Channel Zero Cross Detector
1 = Change gain on zero cross only
0 = Change gain immediately
5:0
LINVOL
[5:0]
010111
( 0dB )
Left Channel Input Volume Control
111111 = +30dB
111110 = +29.25dB
. . 0.75dB steps down to
000000 = -17.25dB



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