WM8750CLSEFLSLASHR datasheet(46/65 Pages) WOLFSON

46 / 65 page

WM8750L

Production Data

PD, Rev 4.4, August 2012

The BCM generator uses the ADCLRC signal, hence the ADCLRC signal must be enabled when

using bit clock mode. To enable the ADCLRC signal, either the ADC must be powered up or, if the

ADC is not in use, the LRCM bit must be set to enable both the ADCLRC and DACLRC signals when

either the ADC or the DAC is enabled.

Note that, when the BCM function is enabled, the following restrictions apply:

1. The bit clock invert (BCLKINV) function is not available.

2. The DAC and ADC must be operated at the same sample rate.

3. DSP Mode-B digital audio interface mode is not available and must not be selected.

Figure 25 Bit Clock Mode

Note: The shaded bit clock cycles are present only when 24-bit mode is selected. Please refer to the

"Bit Clock Mode" description for details.

CLOCK OUTPUT

By default ADCLRC (pin 9) is the ADC word clock input/output. Under the control of ADCLRM[1:0],

or 11 then ADCLRC pin is always an output even in slave mode or when TRI = ‘1’, (see Table 38).

The ADC then uses the DACLRC pin as its LRCLK in both master and slave modes.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R27(1Bh)

Additional

Control (3)

8:7

ADCLRM

[1:0]

Configures ADCLRC pin

00 = ADCLRC is ADC word clock input (slave

mode) or ADCLRC output (master mode)

01 = ADCLRC pin is MCLK output

10 = ADCLRC pin is MCLK / 5.5 output

11 = ADCLRC pin is MCLK / 6 output

Table 38 ADCLRC Clock Output

WM8750CLSEFL/R Datasheet(PDF) 46 Page - Wolfson Microelectronics plc