WM8750CLSEFLSLASHR datasheet(26/65 Pages) WOLFSON

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WM8750L

Production Data

PD, Rev 4.4, August 2012

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R17 (11h)

ALC Control 1

8:7

ALCSEL

[1:0]

(OFF)

ALC function select

00 = ALC off (PGA gain set by register)

01 = Right channel only

10 = Left channel only

11 = Stereo (PGA registers unused)

Note: ensure that LINVOL and

RINVOL settings (reg. 0 and 1) are

the same before entering this mode.

6:4

MAXGAIN

[2:0]

111

(+30dB)

Set Maximum Gain of PGA

111 : +30dB

110 : +24dB

….(-6dB steps)

001 : -6dB

000 : -12dB

3:0

ALCL

[3:0]

1011

(-12dB)

ALC target – sets signal level at ADC

input

0000 = -28.5dB fs

0001 = -27.0dB fs

… (1.5dB steps)

1110 = -7.5dB fs

1111 = -6dB fs

R18 (12h)

ALC Control 2

ALCZC

0 (zero

cross off)

ALC uses zero cross detection circuit.

3:0

HLD

[3:0]

0000

(0ms)

ALC hold time before gain is increased.

0000 = 0ms

0001 = 2.67ms

0010 = 5.33ms

… (time doubles with every step)

1111 = 43.691s

R19 (13h)

ALC Control 3

7:4

DCY

[3:0]

0011

(192ms)

ALC decay (gain ramp-up) time

0000 = 24ms

0001 = 48ms

0010 = 96ms

… (time doubles with every step)

1010 or higher = 24.58s

3:0

ATK

[3:0]

0010

(24ms)

ALC attack (gain ramp-down) time

0000 = 6ms

0001 = 12ms

0010 = 24ms

… (time doubles with every step)

1010 or higher = 6.14s

Table 13 ALC Control

Note: For correct ALC operation in differential input mode, it is recommended that the combined

signal gain (mic boost and PGA) does not exceed 30dB when the ALC is enabled.

WM8750CLSEFL/R Datasheet(PDF) 26 Page - Wolfson Microelectronics plc

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