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Z8018010VSC Datasheet(PDF) 63 Page - Zilog, Inc. |
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Z8018010VSC Datasheet(HTML) 63 Page - Zilog, Inc. |
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63 / 85 page  Z80180 Microprocessor Unit 57 PS014004-1106 Architecture In the R1 and Z Mask, these DMA registers are expanded from 4 bits to 3 bits in the package version of CP-68. DMA Byte Count Register Channel 0 (BCRO: I/O ADDRESS = 26h to 27h) specifies the number of bytes to be transferred. This reg- ister contains 16 bits and may specify up to 64 KB transfers. When one byte is transferred, the register is decremented by 1. If n bytes are transferred, n must be stored before the DMA operation. All DMA Count Register channels are undefined during RESET. DMA Byte Count Register Channel 0L Mnemonic BCR0L: Address 26h Figure 54. DMA Byte Count Register 0L Table 15. DMA Transfer Requests A19* A18 A17 A16 DMA Transfer Request X X 00DREQ0 X X 01TDR0 (ASCI0) X X 10TDR1 (ASCI1) X X 11Not Used DMA Byte Count Register Note: Note: 7 6 54 32 1 0 Counting Data |
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