Z8018010VSC datasheet(22/85 Pages) ZILOG

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Z80180

Microprocessor Unit

PS014004-1106

Architecture

On the Z80180, this choice makes the processor fetch a RETI instruction one time only, and

when fetching a RETI from zero-wait-state memory uses three clock machine cycles, which

are not fully Z80-timing compatible but are compatible with the on-chip CTCs.

When M1E = 0, the processor does not drive M1 Low during instruction fetch cycles. After

fetching a RETI instruction one time only, with normal timing, the processor goes back and

refetches the instruction using fully Z80-compatible cycles that include driving M1 Low.

Some external Z80 peripherals may require properly decoded RETI instructions. Figure 9

illustrates the RETI sequence when M1E = 0.

Figure 9. RETI Instruction Sequence with MIE = 0

M1TE (M1 Temporary Enable)—

This bit controls the temporary

assertion of the M1 signal. It is always read back as a 1 and is set to 1 during RESET.

When M1E is set to 0 to accommodate certain external Z80 peripheral(s), those same

device(s) may require a pulse on M1 after programming certain of their registers to complete

the function being programmed.

For example, when a control word is written to the Z80 PIO to enable interrupts, no enable

actually takes place until the PIO identifies an active M1 signal. When M1TE = 1, there is no

change in the operation of the M1

signal and M1E controls its function. When M1TE = 0, the M1 output is asserted during the

next opcode fetch cycle regardless of the state

programmed into the M1E bit. This instance is only momentary (one time only) and you are

not required to preprogram a 1 to disable the function (see Figure 10).

A0–A18 (A19)

D0–D7

PC+1

EDh

4Dh

EDh

4Dh

MREQ

Z8018010VSC Datasheet(PDF) 22 Page - Zilog, Inc.