Z8018010VSC datasheet(48/85 Pages) ZILOG

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Z80180

Microprocessor Unit

PS014004-1106

Architecture

MPE

is reset to 0, all bytes, regardless of the state of the MPB data bit, affect the REDR and

error flags. MPE is cleared to 0 during RESET.

RE: Receiver Enable (bit 6)—

When RE is set to 1, the ASCI transmitter is enabled. When

is reset to 0, the transmitter is disables and any transmit operation in progress is

interrupted. However, the TDRE flag is not reset and the previous contents of TDRE are held.

is cleared to 0 in IOSTOP mode during RESET.

TE: Transmitter Enable (bit 5)—

When TE is set to 1, the ASCI receiver is enabled. When

is reset to 0, the transmitter is disabled and any transmit operation in progress is

interrupted. However, the TDRE flag is not reset and the previous contents of TDRE are held.

is cleared to 0 in IOSTOP mode during RESET.

RTS0: Request to Send Channel 0 (bit 4 in CNTLA0 only)—

If bit 4 of the System

Configuration Register is 0, the RTS0/TxS pin features the RTS0 function. RTS0 allows the

ASCI to control (START/STOP) another communication devices transmission (for example,

by connecting to that device’s CTS input). RTS0 is essentially a 1 bit output port, having no

side effects on other ASCI registers or flags. Bit 4 in CNTLA1 is not used.

MPBR/EFR: Multiprocessor Bit Receive/Error Flag Reset (bit 3)—

When multiprocessor

mode is enabled (MP in CNTLB = 1), MPBR, when read, contains the value of the MPB bit for

the most recent receive operation. When written to 0, the EFR function is selected to reset all

error flags (OVRN, FE, PE and BRK in the ASEXT register) to 0. MPBR/EFR is undefined

during RESET.

MOD2, 1, 0: ASCI Data Format Mode 2, 1, 0 (bits 2–0)—

These bits program the ASCI

data format as listed in Table 10.

The data formats available based on all combinations of MOD2, MOD1, and MOD0 are

indicated in Table 11.

Table 10. ASCI Data Formats Mode 2, 1, 0

Bit

Description

MOD2 = 0

→7 bit data

MOD2 = 1

→8 bit data

MOD1 = 0

→No parity

MOD1 = 1

→Parity enabled

MOD0 = 0

→1 stop bit

MOD0 = 1

→2 stop bits

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