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Z8018010VSC Datasheet(PDF) 28 Page - Zilog, Inc. |
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Z8018010VSC Datasheet(HTML) 28 Page - Zilog, Inc. |
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28 / 85 page ![]() Z80180 Microprocessor Unit 22 PS014004-1106 Architecture AC Characteristics Table 7, Table 8, and Table 9 provide AC characteristics for the Z80180-6, Z80180-8, and Z80180-10, respectively. VCC = 5 V + 10%, VSS = 0 V, TA – 0 °C to +70 °C, unless otherwise noted. CP Pin Capacitance VINVin = 0V, φ = 1 MHz TA = 25° C –– 12 pF Note: *VIHmin = VCC –1.0 V, VILmax = 0.8 V (all output terminals are at no load); VCC = 5.0 V. **VCC = 5 V + 10%, VSS = 0 V over specified temperature range, unless otherwise noted Table 7. Z80180-6 AC Characteristics No Symbol Item Z80180-6 Unit Min Max 1tcyc Clock Cycle Time 162 2000 ns 2tCHW Clock H Pulse Width 65 – ns 3tCLW Clock L Pulse Width 65 – ns 4tcf Clock Fall Time – 15 ns 5tcr Clock Rise Time – 15 ns 6tAD ØRise to Address Valid Delay – 90 ns 7tAS Address Valid to MREQ Fall or IORQ Fall) 30 – ns 8tMED1 Ø Fall to MREQ Fall Delay – 60 ns 9tRDD1 Ø Fall to RD Fall Delay IOC = 1 – 60 ns Ø Rise to RD Rise Delay IOC = 0 – 65 10 tM1D1 Ø Rise to M1 Fall Delay – 80 ns 11 tAH Address Hold Time from (MREQ, IOREQ, RD, WR) 35 – ns 12 tMED2 Ø Fall to MREQ Rise Delay – 60 ns 13 tRDD2 Ø Fall to RD Rise Delay – 60 ns 14 tM1D2 Ø Rise to M1 Rise Delay – 80 ns 15 tDRS Data Read Set-up Time 40 – ns 16 tDRH Data Read Hold Time 0 – ns 17 tSTD1 Ø Fall to ST Fall Delay – 90 ns 18 tSTD2 Ø Fall to ST Rise Delay – 90 ns 19 tWS WAIT Set-up Time to Ø Fall 40 – ns Table 6. DC Characteristics (continued) Symbol Item Condition Min Typ Max Unit |
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