Z8018010VSC datasheet(29/85 Pages) ZILOG

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Z80180

Microprocessor Unit

PS014004-1106

Architecture

tWH

WAIT Hold Time from Ø Fall

–

tWDZ

Ø Rise to Data Float Delay

–

tWRD1 Ø Rise to WR Fall Delay

–

tWDD

Ø Fall to WRITE Data Delay Time

–

tWDS

WRITE Data Set-up Time to WR Fall

–

tWRD2 Ø Fall to WR Rise Delay

–

tWRP

WR Pulse Width

170

–

26a

WR Pulse Width (I/O WRITE Cycle)

332

–

tWDH

WRITE Data Hold Time from (WR Rise

)

–

tIOD1

Ø Fall to IORQ Fall Delay

IOC = 1

–

Ø Rise to IORQ Fall Delay

IOC = 1

–

tIOD2

Ø Fall to IORQ Rise Delay

–

tIOD3

M1 Fall to IORQ Fall Delay

340

–

tINTS

INT Set-up Time to Ø Fall

–

tINTS

INT Hold Time from Ø Fall

–

tNMIW

NMI Pulse Width

120

–

tBRS

BUSREQ Set-up Time to Ø Fall

–

tBRH

BUSREQ Hold Time from Ø Fall

–

tBAD1

Ø Rise to BUSACK Fall Delay

–

tBAD2

Ø Fall to BUSACK Rise Delay

–

tBZD

Ø Rise to Bus Floating Delay Time

–

125

tMEWH MREQ Pulse Width (High)

110

–

tMEWL MREQ Pulse Width (Low)

125

–

tRFD1

Ø Rise to RFSH Fall Delay

–

tRFD2

Ø Rise to RFSH Rise Delay

–

tHAD1

Ø Rise to HALT Fall Delay

–

tHAD2

Ø Rise to HALT Rise Delay

–

tDRQS /DREQi Set-up Time to Ø Rise

–

tDRQH /DREQi Hold Time from Ø Rise

–

tTED1

Ø Fall to TENDi Fall Delay

–

tTED2

Ø Fall to TENDi Rise Delay

–

tED1

Ø Rise to E Rise Delay

–

tED2

Ø Fall or Rise to E Fall Delay

–

PWEH

E Pulse Width (High)

–

PWEL

E Pulse Width (Low)

180

–

tEr

Enable Rise Time

–

tEf

Enable Fall Time

–

Table 7. Z80180-6 AC Characteristics (continued)

Symbol Item

Z80180-6

Unit

Min

Max

Z8018010VSC Datasheet(PDF) 29 Page - Zilog, Inc.

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