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Z8018010VSC Datasheet(PDF) 23 Page - Zilog, Inc.

Part # Z8018010VSC
Description  Microprocessor Unit
PDF  85 Pages
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Manufacturer  ZILOG [Zilog, Inc.]
Direct Link  http://www.zilog.com
Logo ZILOG - Zilog, Inc.

Z8018010VSC Datasheet(HTML) 23 Page - Zilog, Inc.

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Z80180
Microprocessor Unit
17
PS014004-1106
Architecture
Figure 10. M1 Temporary Enable Timing
IOC—
This bit controls the timing of the IORQ and RD signals. It is set to 1 by RESET. When
IOC = 1
, the IORQ and RD signals function the same as the Z64180 (Figure 11).
Figure 11. I/O READ and WRITE Cycles with IOC = 1
When IOC = 0, the timing of the IORQ and RD signals match the timing of the Z80. The
IORQ
and RD signals go active as a result of the rising edge of T2 (see Figure 12).
Figure 12. I/O READ and WRITE Cycles with IOC = 0
T1
T2
T3
T1
T2
T3
f
WR
M1
Opcode Fetch
WRITE into OMCR
T1
T2
TW
T3
φ
IORQ
RD
WR
T1
T2
TW
T3
φ
IORQ
RD
WR



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