30F4013 datasheet(220/228 Pages) MICROCHIP

220 / 228 page

dsPIC30F3014/4013

DS70138G-page 220

 2010 Microchip Technology Inc.

Round Logic ................................................................ 22

Write-Back .................................................................. 22

Data Address Space ........................................................... 30

Alignment .................................................................... 32

Alignment (Figure) ...................................................... 32

Effect of Invalid Memory Accesses (Table)................. 32

MCU and DSP (MAC Class) Instructions Example..... 31

Memory Map ............................................................... 30

Near Data Space ........................................................ 33

Software Stack ............................................................ 33

Spaces ........................................................................ 32

Width ........................................................................... 32

Data Converter Interface (DCI) Module ............................ 121

Data EEPROM Memory ...................................................... 49

Erasing ........................................................................ 50

Erasing, Block ............................................................. 50

Erasing, Word ............................................................. 50

Protection Against Spurious Write .............................. 52

Reading....................................................................... 49

Write Verify ................................................................. 52

Writing ......................................................................... 51

Writing, Block .............................................................. 51

Writing, Word .............................................................. 51

DC Characteristics ............................................................ 172

BOR .......................................................................... 180

I/O Pin Input Specifications ....................................... 178

I/O Pin Output Specifications .................................... 178

Idle Current (IIDLE) .................................................... 175

LVDL ......................................................................... 179

Operating Current (IDD)............................................. 174

Power-Down Current (IPD) ........................................ 176

Program and EEPROM............................................. 180

Temperature and Voltage Specifications .................. 172

DCI Module

Bit Clock Generator................................................... 125

Buffer Alignment with Data Frames .......................... 127

Buffer Control ............................................................ 121

Buffer Data Alignment ............................................... 121

Buffer Length Control ................................................ 127

COFS Pin .................................................................. 121

CSCK Pin .................................................................. 121

CSDI Pin ................................................................... 121

CSDO Mode Bit ........................................................ 128

CSDO Pin ................................................................. 121

Data Justification Control Bit ..................................... 126

Device Frequencies for Common Codec CSCK Frequen-

cies (Table) ....................................................... 125

Digital Loopback Mode ............................................. 128

Enable ....................................................................... 123

Frame Sync Generator ............................................. 123

Frame Sync Mode Control Bits ................................. 123

I/O Pins ..................................................................... 121

Interrupts ................................................................... 128

Introduction ............................................................... 121

Master Frame Sync Operation .................................. 123

Operation .................................................................. 123

Operation During CPU Idle Mode ............................. 128

Operation During CPU Sleep Mode .......................... 128

Receive Slot Enable Bits........................................... 126

Receive Status Bits ................................................... 127

Sample Clock Edge Control Bit................................. 126

Slave Frame Sync Operation .................................... 124

Slot Enable Bits Operation with Frame Sync ............ 126

Slot Status Bits.......................................................... 128

Synchronous Data Transfers .................................... 126

Timing Requirements

AC-Link Mode ................................................... 195

Multichannel, I2S Modes................................... 193

Transmit Slot Enable Bits ......................................... 126

Transmit Status Bits.................................................. 127

Transmit/Receive Shift Register ............................... 121

Underflow Mode Control Bit...................................... 128

Word-Size Selection Bits .......................................... 123

Development Support ....................................................... 167

Device Configuration

Device Configuration Registers

FBORPOR ................................................................ 156

FGS .......................................................................... 156

FOSC........................................................................ 156

FWDT ....................................................................... 156

Device Overview................................................................. 11

Disabling the UART .......................................................... 105

Divide Support .................................................................... 18

Instructions (Table) ..................................................... 18

DSP Engine ........................................................................ 19

Multiplier ..................................................................... 21

Dual Output Compare Match Mode .................................... 86

Continuous Pulse Mode.............................................. 86

Single Pulse Mode...................................................... 86

Electrical Characteristics .................................................. 171

AC............................................................................. 180

DC ............................................................................ 172

Enabling and Setting Up UART

Alternate I/O ............................................................. 105

Enabling and Setting up UART

Setting up Data, Parity and Stop Bit Selections........ 105

Enabling the UART ........................................................... 105

Equations

ADC Conversion Clock ............................................. 133

Baud Rate................................................................. 107

Bit Clock Frequency.................................................. 125

COFSG Period.......................................................... 123

Serial Clock Rate ........................................................ 96

Time Quantum for Clock Generation ........................ 117

Errata .................................................................................... 9

Exception Sequence

Trap Sources .............................................................. 62

External Clock Timing Requirements ............................... 182

Type A Timer ............................................................ 188

Type B Timer ............................................................ 189

Type C Timer ............................................................ 189

External Interrupt Requests ................................................ 64

Fast Context Saving ........................................................... 64

Flash Program Memory ...................................................... 43

I/0 Ports

I/O Pin Specifications

Input.......................................................................... 178

Output ....................................................................... 178

I/O Ports.............................................................................. 53

Parallel (PIO) .............................................................. 53

I2C 10-Bit Slave Mode Operation ....................................... 93

Reception ................................................................... 94

30F4013 Datasheet(PDF) 220 Page - Microchip Technology

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