30F4013 datasheet(129/228 Pages) MICROCHIP

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 2010 Microchip Technology Inc.

DS70138G-page 129

dsPIC30F3014/4013

18.6.2

20-BIT AC-LINK MODE

The 20-bit AC-Link mode allows all bits in the data time

slots to be transmitted and received but does not main-

tain data alignment in the TXBUF and RXBUF

registers.

The 20-bit AC-Link mode functions similar to the Multi-

channel mode of the DCI module, except for the duty

cycle of the Frame Synchronization signal. The AC-

Link Frame Synchronization signal should remain high

for 16 CSCK cycles and should be low for the following

240 cycles.

The 20-bit mode treats each 256-bit AC-Link frame as

sixteen, 16-bit time slots. In the 20-bit AC-Link mode,

the module operates as if COFSG<3:0> = 1111 and

WS<3:0> = 1111. The data alignment for 20-bit data

slots is ignored. For example, an entire AC-Link data

frame can be transmitted and received in a packed

fashion by setting all bits in the TSCON and RSCON

SFRs. Since the total available buffer length is 64 bits,

it would take 4 consecutive interrupts to transfer the

AC-Link frame. The application software must keep

track of the current AC-Link frame segment.

18.7

I2S Mode Operation

The DCI module is configured for I2S mode by writing

a value of ‘01’ to the COFSM<1:0> control bits in the

DCICON1 SFR. When operating in the I2S mode, the

DCI module generates Frame Synchronization signals

with a 50% duty cycle. Each edge of the Frame

Synchronization signal marks the boundary of a new

data word transfer.

The user must also select the frame length and data

word size using the COFSG and WS control bits in the

DCICON2 SFR.

18.7.1

I2S FRAME AND DATA WORD

LENGTH SELECTION

The WS and COFSG control bits are set to produce the

period for one half of an I2S data frame. That is, the

frame length is the total number of CSCK cycles

required for a left or a right data word transfer.

The BLEN bits must be set for the desired buffer length.

Setting BLEN<1:0> = 01 produces a CPU interrupt,

once per I2S frame.

18.7.2

I2S DATA JUSTIFICATION

As per the I2S specification, a data word transfer, by

default, begins one CSCK cycle after a transition of the

WS signal. A ‘MSb left justified’ option can be selected

using the DJST control bit in the DCICON1 SFR.

If DJST = 1, the I2S data transfers are MSb left justified.

The MSb of the data word is presented on the CSDO

pin during the same CSCK cycle as the rising or falling

edge of the COFS signal. The CSDO pin is tri-stated

after the data word has been sent.

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