PIC18F1220ESLASHSOSQTP datasheet(201/308 Pages) MICROCHIP

201 / 308 page

DS39605F-page 199

PIC18F1220/1320

ANDWF

AND W with f

Syntax:

[ label ] ANDWF

f [,d [,a]]

Operands:

≤ f ≤ 255

∈ [0,1]

Operation:

(W) .AND. (f)

→ dest

Status Affected:

N, Z

Encoding:

0001

01da

ffff

Description:

The contents of W are AND’ed with

stored in W. If ‘d’ is ‘1’, the result is

stored back in register ‘f’ (default).

If ‘a’ is ‘0’, the Access Bank will be

selected. If ‘a’ is ‘1’, the BSR will

not be overridden (default).

Words:

Cycles:

Q Cycle Activity:

Decode

Read

Process

Data

Write to

destination

Example:

ANDWF

REG,

Before Instruction

0x17

REG

0xC2

After Instruction

0x02

REG

0xC2

Branch if Carry

Syntax:

[ label ] BC

Operands:

-128

≤ n ≤ 127

Operation:

if Carry bit is ‘1’

(PC) + 2 + 2n

→ PC

Status Affected:

None

Encoding:

1110

0010

nnnn

Description:

If the Carry bit is ‘1’, then the

program will branch.

The 2’s complement number ‘2n’ is

added to the PC. Since the PC will

have incremented to fetch the next

instruction, the new address will be

PC + 2 + 2n. This instruction is then

a two-cycle instruction.

Words:

Cycles:

1(2)

Q Cycle Activity:

If Jump:

Decode

Read literal

‘n’

Process

Data

Write to PC

operation

If No Jump:

Decode

Read literal

‘n’

Process

Data

operation

Example:

HERE

JUMP

Before Instruction

address (HERE)

After Instruction

If Carry

address (JUMP)

If Carry

address (HERE + 2)

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