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PIC18F1220E/SOSQTP Datasheet(PDF) 39 Page - Microchip Technology |
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PIC18F1220E/SOSQTP Datasheet(HTML) 39 Page - Microchip Technology |
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39 / 308 page  © 2007 Microchip Technology Inc. DS39605F-page 37 PIC18F1220/1320 BSR 1220 1320 ---- 0000 ---- 0000 ---- uuuu INDF2 1220 1320 N/A N/A N/A POSTINC2 1220 1320 N/A N/A N/A POSTDEC2 1220 1320 N/A N/A N/A PREINC2 1220 1320 N/A N/A N/A PLUSW2 1220 1320 N/A N/A N/A FSR2H 1220 1320 ---- 0000 ---- 0000 ---- uuuu FSR2L 1220 1320 xxxx xxxx uuuu uuuu uuuu uuuu STATUS 1220 1320 ---x xxxx ---u uuuu ---u uuuu TMR0H 1220 1320 0000 0000 0000 0000 uuuu uuuu TMR0L 1220 1320 xxxx xxxx uuuu uuuu uuuu uuuu T0CON 1220 1320 1111 1111 1111 1111 uuuu uuuu OSCCON 1220 1320 0000 q000 0000 q000 uuuu qquu LVDCON 1220 1320 --00 0101 --00 0101 --uu uuuu WDTCON 1220 1320 ---- ---0 ---- ---0 ---- ---u RCON(4) 1220 1320 0--1 11q0 0--q qquu u--u qquu TMR1H 1220 1320 xxxx xxxx uuuu uuuu uuuu uuuu TMR1L 1220 1320 xxxx xxxx uuuu uuuu uuuu uuuu T1CON 1220 1320 0000 0000 u0uu uuuu uuuu uuuu TMR2 1220 1320 0000 0000 0000 0000 uuuu uuuu PR2 1220 1320 1111 1111 1111 1111 1111 1111 T2CON 1220 1320 -000 0000 -000 0000 -uuu uuuu ADRESH 1220 1320 xxxx xxxx uuuu uuuu uuuu uuuu ADRESL 1220 1320 xxxx xxxx uuuu uuuu uuuu uuuu ADCON0 1220 1320 00-0 0000 00-0 0000 uu-u uuuu ADCON1 1220 1320 -000 0000 -000 0000 -uuu uuuu ADCON2 1220 1320 0-00 0000 0-00 0000 u-uu uuuu CCPR1H 1220 1320 xxxx xxxx uuuu uuuu uuuu uuuu CCPR1L 1220 1320 xxxx xxxx uuuu uuuu uuuu uuuu CCP1CON 1220 1320 0000 0000 0000 0000 uuuu uuuu PWM1CON 1220 1320 0000 0000 0000 0000 uuuu uuuu ECCPAS 1220 1320 0000 0000 0000 0000 uuuu uuuu TABLE 4-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets WDT Reset RESET Instruction Stack Resets Wake-up via WDT or Interrupt Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Shaded cells indicate conditions do not apply for the designated device. Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table 4-2 for Reset value for specific condition. 5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the Oscillator mode selected. When not enabled as PORTA pins, they are disabled and read ‘0’. 6: Bit 5 of PORTA is enabled if MCLR is disabled. |
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