PIC18F1220ESLASHSOSQTP datasheet(61/308 Pages) MICROCHIP

61 / 308 page

DS39605F-page 59

PIC18F1220/1320

EECON1 REGISTER

R/W-x

U-0

R/W-0

R/W-x

R/W-0

R/S-0

EEPGD

CFGS

—

FREE

WRERR

WREN

bit 7

bit 0

bit 7

EEPGD: Flash Program or Data EEPROM Memory Select bit

= Access program Flash memory

= Access data EEPROM memory

bit 6

CFGS: Flash Program/Data EE or Configuration Select bit

= Access configuration registers

= Access program Flash or data EEPROM memory

bit 5

Unimplemented: Read as ‘0’

bit 4

FREE: Flash Row Erase Enable bit

= Erase the program memory row addressed by TBLPTR on the next WR command

(cleared by completion of erase operation – TBLPTR<5:0> are ignored)

= Perform write only

bit 3

WRERR: EEPROM Error Flag bit

= A write operation was prematurely terminated (any Reset during self-timed programming)

= The write operation completed normally

Note:

When a WRERR occurs, the EEPGD and CFGS bits are not cleared. This allows

tracing of the error condition.

bit 2

WREN: Write Enable bit

= Allows erase or write cycles

= Inhibits erase or write cycles

bit 1

WR: Write Control bit

= Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write cycle.

(The operation is self-timed and the bit is cleared by hardware once write is complete. The

WR bit can only be set (not cleared) in software.)

= Write cycle completed

bit 0

RD: Read Control bit

= Initiates a memory read

(Read takes one cycle. RD is cleared in hardware. The RD bit can only be set (not cleared)

in software. RD bit cannot be set when EEPGD = 1.)

= Read completed

Legend:

R = Readable bit

S = Settable only

U = Unimplemented bit, read as ‘0’

W = Writable bit

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

PIC18F1220E/SOSQTP Datasheet(PDF) 61 Page - Microchip Technology

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