PIC18F1220ESLASHSOSQTP datasheet(92/308 Pages) MICROCHIP

92 / 308 page

PIC18F1220/1320

DS39605F-page 90

10.2

PORTB, TRISB and LATB

Registers

PORTB is an 8-bit wide, bidirectional port. The corre-

sponding data direction register is TRISB. Setting a

TRISB bit (= 1) will make the corresponding PORTB

pin an input (i.e., put the corresponding output driver in

a high-impedance mode). Clearing a TRISB bit (= 0)

will make the corresponding PORTB pin an output (i.e.,

put the contents of the output latch on the selected pin).

The Data Latch register (LATB) is also memory

mapped. Read-modify-write operations on the LATB

PORTB.

EXAMPLE 10-2:

INITIALIZING PORTB

Pins RB0-RB2 are multiplexed with INT0-INT2; pins

RB0, RB1 and RB4 are multiplexed with A/D inputs;

pins RB1 and RB4 are multiplexed with EUSART; and

pins RB2, RB3, RB6 and RB7 are multiplexed with

ECCP.

Each of the PORTB pins has a weak internal pull-up. A

single control bit can turn on all the pull-ups. This is

performed by clearing bit, RBPU (INTCON2<7>). The

weak pull-up is automatically turned off when the port

pin is configured as an output. The pull-ups are

disabled on a Power-on Reset.

Four of the PORTB pins (RB7:RB4) have an interrupt-

on-change feature. Only pins configured as inputs can

cause this interrupt to occur (i.e., any RB7:RB4 pin

configured as an output is excluded from the interrupt-

on-change comparison). The input pins (of RB7:RB4)

are compared with the old value latched on the last

read of PORTB. The “mismatch” outputs of RB7:RB4

are OR’ed together to generate the RB Port Change

Interrupt with Flag bit, RBIF (INTCON<0>).

This interrupt can wake the device from Sleep. The

user, in the Interrupt Service Routine, can clear the

interrupt in the following manner:

Any read or write of PORTB (except with the

MOVFF

instruction). This will end the mismatch

condition.

Clear flag bit, RBIF.

A mismatch condition will continue to set flag bit, RBIF.

Reading PORTB will end the mismatch condition and

allow flag bit, RBIF, to be cleared.

The interrupt-on-change feature is recommended for

wake-up on key depression operation and operations

where PORTB is only used for the interrupt-on-change

feature. Polling of PORTB is not recommended while

using the interrupt-on-change feature.

FIGURE 10-7:

BLOCK DIAGRAM OF

RB0/AN4/INT0 PIN

Note:

On a Power-on Reset, RB4:RB0 are

configured as analog inputs by default and

read as ‘0’; RB7:RB5 are configured as

digital inputs.

CLRF

PORTB

; Initialize PORTB by

; clearing output

; data latches

CLRF

LATB

; Alternate method

; to clear output

; data latches

MOVLW

0x70

; Set RB0, RB1, RB4 as

MOVWF

ADCON1

; digital I/O pins

MOVLW

0xCF

; Value used to

; initialize data

; direction

MOVWF

TRISB

; Set RB<3:0> as inputs

; RB<5:4> as outputs

; RB<7:6> as inputs

Data Latch

RBPU(2)

VDD

Data Bus

WR LATB

WR TRISB

RD TRISB

RD PORTB

Weak

Pull-up

INTx

I/O

pin(1)

Schmitt Trigger

Buffer

TRIS Latch

RD LATB

or PORTB

Note 1:

I/O pins have diode protection to VDD and VSS.

To enable weak pull-ups, set the appropriate TRIS

bit(s) and clear the RBPU bit (INTCON2<7>).

To A/D Converter

Analog Input Mode

TTL

Input

Buffer

PIC18F1220E/SOSQTP Datasheet(PDF) 92 Page - Microchip Technology

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