PIC18F1220ESLASHSOSQTP datasheet(72/308 Pages) MICROCHIP

72 / 308 page

PIC18F1220/1320

DS39605F-page 70

7.7

Operation During Code-Protect

Data EEPROM memory has its own code-protect bits in

configuration

words.

External

read

and

write

operations are disabled if either of these mechanisms

are enabled.

The microcontroller itself can both read and write to the

internal data EEPROM, regardless of the state of the

code-protect configuration bit. Refer to Section 19.0

“Special Features of the CPU” for additional

information.

7.8

Using the Data EEPROM

The data EEPROM is a high endurance, byte address-

able array that has been optimized for the storage of fre-

quently changing information (e.g., program variables or

other data that are updated often). Frequently changing

values will typically be updated more often than specifi-

cation D124. If this is not the case, an array refresh must

be performed. For this reason, variables that change

infrequently (such as constants, IDs, calibration, etc.)

should be stored in Flash program memory.

A simple data EEPROM refresh routine is shown in

Example 7-3.

EXAMPLE 7-3:

DATA EEPROM REFRESH ROUTINE

TABLE 7-1:

REGISTERS ASSOCIATED WITH DATA EEPROM MEMORY

Note:

If data EEPROM is only used to store

constants and/or data that changes rarely,

an array refresh is likely not required. See

specification D124.

CLRF

EEADR

; Start at address 0

BCF

EECON1, CFGS

; Set for memory

BCF

EECON1, EEPGD

; Set for Data EEPROM

BCF

INTCON, GIE

; Disable interrupts

BSF

EECON1, WREN

; Enable writes

Loop

; Loop to refresh array

BSF

EECON1, RD

; Read current address

MOVLW

55h

;

MOVWF

EECON2

; Write 55h

MOVLW

AAh

;

MOVWF

EECON2

; Write AAh

BSF

EECON1, WR

; Set WR bit to begin write

BTFSC

EECON1, WR

; Wait for write to complete

BRA

$-2

INCFSZ

EEADR, F

; Increment address

BRA

Loop

; Not zero, do it again

BCF

EECON1, WREN

; Disable writes

BSF

INTCON, GIE

; Enable interrupts

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on:

POR, BOR

Value on

all other

Resets

INTCON

GIE/GIEH

PEIE/GIEL

TMR0IE

INTE

RBIE

TMR0IF

INTF

RBIF

0000 000x

0000 000u

EEADR

EEPROM Address Register

0000 0000

EEDATA

EEPROM Data Register

0000 0000

EECON2

EEPROM Control Register 2 (not a physical register)

—

EECON1

EEPGD

CFGS

—

FREE

WRERR

WREN

xx-0 x000

uu-0 u000

IPR2

OSCFIP

—

—EEIP

—

LVDIP

TMR3IP

—

1--1 -11-

PIR2

OSCFIF

—

—EEIF

—

LVDIF

TMR3IF

—

0--0 -00-

PIE2

OSCFIE

—

—EEIE

—

LVDIE

TMR3IE

—

0--0 -00-

Legend: x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used during Flash/EEPROM access.

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