PIC18F1220ESLASHSOSQTP datasheet(64/308 Pages) MICROCHIP

64 / 308 page

PIC18F1220/1320

DS39605F-page 62

6.4

Erasing Flash Program Memory

The minimum erase block size is 32 words or 64 bytes

under firmware control. Only through the use of an

external programmer, or through ICSP control, can

larger blocks of program memory be bulk erased. Word

erase in Flash memory is not supported.

When initiating an erase sequence from the micro-

controller itself, a block of 64 bytes of program memory

is erased. The Most Significant 16 bits of the

TBLPTR<21:6> point to the block being erased.

TBLPTR<5:0> are ignored.

The EECON1 register commands the erase operation.

The EEPGD bit must be set to point to the Flash

program memory. The CFGS bit must be clear to

access program Flash and data EEPROM memory.

The WREN bit must be set to enable write operations.

The FREE bit is set to select an erase operation. The

WR bit is set as part of the required instruction

sequence (as shown in Example 6-2) and starts the

actual erase operation. It is not necessary to load the

TABLAT register with any data as it is ignored.

For protection, the write initiate sequence using

EECON2 must be used.

A long write is necessary for erasing the internal Flash.

Instruction execution is halted while in a long write

cycle. The long write will be terminated by the internal

programming timer.

6.4.1

FLASH PROGRAM MEMORY

ERASE SEQUENCE

The sequence of events for erasing a block of internal

program memory location is:

Load Table Pointer with address of row being

erased.

Set the EECON1 register for the erase operation:

• set EEPGD bit to point to program memory;

• clear the CFGS bit to access program

memory;

• set WREN bit to enable writes;

• set FREE bit to enable the erase.

Disable interrupts.

Write 55h to EECON2.

Write AAh to EECON2.

Set the WR bit. This will begin the row erase

cycle.

The CPU will stall for duration of the erase

(about 2 ms using internal timer).

Execute a NOP.

Re-enable interrupts.

EXAMPLE 6-2:

ERASING A FLASH PROGRAM MEMORY ROW

MOVLW

CODE_ADDR_UPPER

; load TBLPTR with the base

MOVWF

TBLPTRU

; address of the memory block

MOVLW

CODE_ADDR_HIGH

MOVWF

TBLPTRH

MOVLW

CODE_ADDR_LOW

MOVWF

TBLPTRL

ERASE_ROW

BSF

EECON1, EEPGD

; point to FLASH program memory

BSF

EECON1, WREN

; enable write to memory

BSF

EECON1, FREE

; enable Row Erase operation

BCF

INTCON, GIE

; disable interrupts

MOVLW

55h

MOVWF

EECON2

; write 55H

Required

MOVLW

AAh

Sequence

MOVWF

EECON2

; write AAH

BSF

EECON1, WR

; start erase (CPU stall)

NOP

BSF

INTCON, GIE

; re-enable interrupts

PIC18F1220E/SOSQTP Datasheet(PDF) 64 Page - Microchip Technology

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