PIC18F1220ESLASHSOSQTP datasheet(133/308 Pages) MICROCHIP

133 / 308 page

DS39605F-page 131

PIC18F1220/1320

16.0

ENHANCED ADDRESSABLE

UNIVERSAL SYNCHRONOUS

ASYNCHRONOUS RECEIVER

TRANSMITTER (EUSART)

The Enhanced Addressable Universal Synchronous

Asynchronous Receiver Transmitter (EUSART) mod-

ule can be configured as a full-duplex asynchronous

system that can communicate with peripheral devices,

such as CRT terminals and personal computers. It can

also be configured as a half-duplex synchronous

system that can communicate with peripheral devices,

such as

A/D or D/A integrated circuits, serial

EEPROMs, etc.

The

Enhanced

Addressable

USART

module

implements additional features, including automatic

baud rate detection and calibration, automatic wake-up

on Sync Break reception and 12-bit Break character

transmit. These features make it ideally suited for use

in Local Interconnect Network (LIN) bus systems.

The EUSART can be configured in the following

modes:

• Asynchronous (full duplex) with:

- Auto-wake-up on character reception

- Auto-baud calibration

- 12-bit Break character transmission

• Synchronous – Master (half duplex) with

selectable clock polarity

• Synchronous – Slave (half duplex) with selectable

clock polarity

The RB1/AN5/TX/CK/INT1 and RB4/AN6/RX/DT/KBI0

pins must be configured as follows for use with the

Universal

Synchronous

Asynchronous

Receiver

Transmitter:

• SPEN (RCSTA<7>) bit must be set ( = 1),

• PCFG6:PCFG5 (ADCON1<5:6>) must be set ( = 1),

• TRISB<4> bit must be set ( = 1) and

• TRISB<1> bit must be set ( = 1).

The operation of the Enhanced USART module is

controlled through three registers:

• Transmit Status and Control (TXSTA)

• Receive Status and Control (RCSTA)

• Baud Rate Control (BAUDCTL)

These are detailed in on the following pages in

and

respectively.

16.1

Asynchronous Operation in Power

Managed Modes

The EUSART may operate in Asynchronous mode

while the peripheral clocks are being provided by the

internal oscillator block. This makes it possible to

remove the crystal or resonator that is commonly

connected as the primary clock on the OSC1 and

OSC2 pins.

The factory calibrates the internal oscillator block out-

put (INTOSC) for 8 MHz (see Table 22-6). However,

this frequency may drift as VDD or temperature

changes and this directly affects the asynchronous

baud rate. Two methods may be used to adjust the

baud rate clock, but both require a reference clock

source of some kind.

The first (preferred) method uses the OSCTUNE

Adjusting the value in the OSCTUNE register allows for

fine resolution changes to the system clock source (see

Section 3.6 “INTOSC Frequency Drift” for more

information).

The other method adjusts the value in the Baud Rate

Generator (BRG). There may not be fine enough

resolution when adjusting the Baud Rate Generator to

compensate for a gradual change in the peripheral

clock frequency.

Note:

The EUSART control will automatically

reconfigure the pin from input to output as

needed.

PIC18F1220E/SOSQTP Datasheet(PDF) 133 Page - Microchip Technology

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