PIC18F1220ESLASHSOSQTP datasheet(188/308 Pages) MICROCHIP

188 / 308 page

PIC18F1220/1320

DS39605F-page 186

19.5.1

PROGRAM MEMORY

CODE PROTECTION

The program memory may be read to, or written from,

any location using the table read and table write

instructions. The device ID may be read with table

reads. The configuration registers may be read and

written with the table read and table write instructions.

In normal execution mode, the CPn bits have no direct

effect. CPn bits inhibit external reads and writes. A

block of user memory may be protected from table

writes if the WRTn configuration bit is ‘0’. The EBTRn

bits control table reads. For a block of user memory

with the EBTRn bit set to ‘0’, a table read instruction

that executes from within that block is allowed to read.

A table read instruction that executes from a location

outside of that block is not allowed to read and will

result in reading ‘0’s. Figures 19-6 through 19-8

illustrate table write and table read protection.

FIGURE 19-6:

TABLE WRITE (WRTn) DISALLOWED: PIC18F1320

Note:

Code protection bits may only be written to

a ‘0’ from a ‘1’ state. It is not possible to

write a ‘1’ to a bit in the ‘0’ state. Code pro-

tection bits are only set to ‘1’ by a full Chip

Erase or Block Erase function. The full

Chip Erase and Block Erase functions can

only be initiated via ICSP or an external

programmer.

000000h

0001FFh

000200h

000FFFh

001000h

001FFFh

WRTB, EBTRB = 11

WRT0, EBTR0 = 01

TBLWT *

TBLPTR = 0002FFh

PC = 0007FEh

TBLWT *

PC = 0017FEh

Program Memory

Configuration Bit Settings

Results: All table writes disabled to Blockn whenever WRTn = 0

WRT1, EBTR1 = 11

PIC18F1220E/SOSQTP Datasheet(PDF) 188 Page - Microchip Technology

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