IA82510

Data Sheet

Asynchronous Serial Controller

February 25, 2011

IA211001219-05

http://www.Innovasic.com

UNCONTROLLED WHEN PRINTED OR COPIED

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Errata No. 3

Problem:

Setting CLCF to x30, which effectively generates the TX clock from the incoming

SCLK signal, kills all transmits.

Description:

Configuration of PMD inadvertently set so RI function is selected instead of SCLK

function. Original Intel device allows SCLK through anyway, IA82510 suppresses it.

Workaround:

Set correct configuration for PMD allows TX clock generation.

Errata No. 4

Problem:

Receiving streamed data has many framing errors and corrupt data when connected to

some modems.

Description:

Shortened stop bit followed immediately by next start bit does not correctly detect

that start bit.

Workaround:

Configure external modem to transmit two stop bits.

Errata No. 5

Problem:

Transmission of streamed data does not return interrupt.

Description:

Stray read of GIR sets TX FIFO interrupt hold logic, but this logic does not reset

when GER[1] is de-asserted.

Workaround:

Reset logic with write to TX data or avoid stray reads of GIR.

Errata No. 6

Problem:

Receiving streamed data has many framing errors at fast baud rates (divisor=6) through

bad modem lines.

Description:

DPLL is not robust for RXD signal with more than 1/16 bit time of variation.

Workaround:

None.