IA82510-PDW28I-R-01 datasheet(13/25 Pages) INNOVASIC

13 / 25 page

IA82510

Data Sheet

Asynchronous Serial Controller

February 25, 2011

IA211001219-05

http://www.Innovasic.com

UNCONTROLLED WHEN PRINTED OR COPIED

Customer Support:

Page 13 of 25

1-888-824-4184

Table 4. AC Parameters

Parameter

Min

Max

Notes

CLK period

54 ns

250 ns

Divide by Two

CLK period

54 ns

108 ns

No Divide by

CLK Low Time

25 ns

–

CLK High Time

25 ns

–

CLK Rise Time

–

10 ns

Divide by Two

Measured between 0.3 * VDD

and 0.7 * VDD

CLK Fall Time

–

10 ns

Divide by Two

Measured between 0.3 * VDD

and 0.7 * VDD

CLK Rise Time

–

15 ns

No Divide by

CLK Fall Time

–

15 ns

No Divide by

Crystal Frequency

1 Mhz

20 Mhz

–

Reset Width

8 * Clock Period

–

RTS/DTR Low Setup to Reset

inactive

6 * Clock Period

–

RTS/DTR Low Hold after

Reset inactive

–

Clock Period

–20 ns

–

RDn Active Width

2* clock period

+65 ns

–

Address/CSn Setup Time to

RDn Active

7 ns

–

Address/CSn Hold after RDn

Inactive

0 ns

–

RDn or WRn Inactive to Active

Delay

Clock Period

+15 ns

–

Data Out Float Delay after

RDn Inactive

–

40 ns

–

WRn Active Width

2 * Clock Period

+15 ns

–

Address CSn Setup Time to

WRn Active

7 ns

–

Address and CSn hold Time

after WRn

0 ns

–

Data in Setup Time to WRn

Inactive

90 ns

–

Data In Hold Time after WRn

Inactive

12 ns

–

SCLK Period

216 ns

–

16x Clocking Mode

SCLK Period

3500 ns

–

1x Clocking Mode

RXD Setup Time to SCLK High

250 ns

–

RXD Hold Time after SCLK

High

250 ns

–

TXD Valid after SCLK Low

–

170 ns

–

TXD Delay after RXD

–

170 ns

Remote Loopback

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