IA82510

Data Sheet

Asynchronous Serial Controller

February 25, 2011

IA211001219-05

http://www.Innovasic.com

UNCONTROLLED WHEN PRINTED OR COPIED

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Table 7. Summary of Errata (Continued)

Errata

No.

Problem

Ver. 00

Ver. 01

Ver. 02

12

Device fails to reset interrupt signal in auto acknowledge mode

when character is read from RX FIFO.

Exists

Fixed

Fixed

13

RX FIFO locks up unexpectedly just after configuration and

before starting reception.

NA

Exists

Exists

14

Unreliable transmits in AUTO TX mode.

NA

Exists

Exists

7.2

Detail

Errata No. 1

Problem:

Scrambled data during boot code shuts down UART, however device works for

application code.

Description:

The RX FIFO is locked, configuration of all registers is done, then the RX FIFO is

unlocked just before entering loopback mode in both boot and application code before normal

operations begin. Boot code additionally does a blind block read of all registers before normal

operations including two reads from the unwritten RX Data FIFO. RX unlock command is

inadvertently incrementing the write pointer. For boot code, the two reads of RX data cause the

read/write pointers to be permanently out of sync. For application code, the pointers end up

synched to the same location, only because the code waits for four characters before reading. This

ends up causing an RX overrun, but to our favor because the pointers are now synched.

Workaround:

Execute a “Flush RX FIFO” command (via RCM register) after configuration and

block read is complete.

Errata No. 2

Problem:

Device does not operate at 8 MHz in divide-by-one mode.

Description:

System testing revealed this operational deficiency.

Workaround:

Switch to divide-by-two mode using 2X clock input.