GDC21D301A datasheet(11/35 Pages) HYNIX

11 / 35 page

GDC21D301A

4. Block Diagram

The figure 2 shows the internal block diagram of

the GDC21D301A. This chip receives the byte-

parallel/bit-serial

transport

data

from

FEC(Forward-Error-Correction) device, and stores

the whole data into DRAM. After decoding the

transport data in DRAM, it de-multiplexes audio,

video, and auxiliary data packets, and transfers

them into the corresponding decoder devices

through the decoder interface blocks. The host

processor can control the GDC21D301A and

access the decoder devices and DRAM through the

host interface. The GDC21D301A generates PWM

pulses to control the frequency of system clock and

audio clock. The pulse width of PWM can be

programmed by the host processor.

FEC

Interface

TS Buffer

Sync

Detect

TS Header

Decode

Adaptation

Field

Decode

PES

Decode

PID

Memory

Buffer

Memory

Controller

4Mb

DRAM

High-speed

Interface

External

Decoder

Interface

Clock

Control

Host

Interface

VCXO

Transport

Stream

8/16bit

MCU

8/16bit

MCU

FEC

Decoder

Figure 2. The Block Diagram of the Transport Decoder

GDC21D301A Datasheet(PDF) 11 Page - Hynix Semiconductor

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