GDC21D301A datasheet(12/35 Pages) HYNIX

12 / 35 page

GDC21D301A

5. Functional Description

5.1 Forward-Error-Correction (FEC)

Interface

The GDC21D301A can receive Transport Stream

packets in byte-parallel or bit-serial mode. FEC

Interface block gets these TS data, and temporarily

saves them in the internal buffer(TS Buffer).

bit-serial

mode,

F_START

should

activated(high) when the most significant bit or the

first bit of each packet is fed. \ERR_BLOCK pin is

used to indicate valid packet, and D_VALID pin to

indicate valid TS data (it should be deactivated at

parity bits). TS data is fed on the rising edge of

FEC_CLOCK.

5.2 Sync Detector

This

block

searches

the

sync

byte

packet(0x47) at Sync Hysterisis register during

specified time. If it detects correct sync data, then

TS Header Decoder block takes control of

decoding process.

5.3 TS Header Decoder

This block decodes Transport Stream header and

determines if packet should be decoded further by

comparing PID with the values in internal PID

memory. PSI data is stored in external DRAM, and

can be read by the host processor. If high speed out

enable(Hig) bit in PID registers is activated, the

whole corresponding TS data are output to high-

speed ports (refer to Register Description section).

5.4 Adaptation Field Decoder

Refer to the Register Description section

5.5 PES Decoder

This block decodes PES header and de-multiplexes

payload data to appropriate parts (refer to Register

Description section).

Audio and auxiliary data are stored in DRAM,

re-read by the GDC21D301A, and sent to

external decoder. But video data is directly

output to the external decoder.

GDC21D301A Datasheet(PDF) 12 Page - Hynix Semiconductor

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