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GDC21D301A Datasheet(PDF) 31 Page - Hynix Semiconductor

Part # GDC21D301A
Description  Transport Decoder
PDF  35 Pages
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Manufacturer  HYNIX [Hynix Semiconductor]
Direct Link  http://www.skhynix.com/kor/main.do
Logo HYNIX - Hynix Semiconductor

GDC21D301A Datasheet(HTML) 31 Page - Hynix Semiconductor

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GDC21D301A
7.4.3 Reset Signal Requirement
\RESET
tRSTw
PARAMETER
PARAMETER
MIN
TYP
MAX
UNIT
tRSTw
RESET pulse width
tCLOCKp
-
-
ns
The low pulse width of reset signal should be larger than tCLCOKp, the operating clock period.
7.4.4 Audio/Video/Data Decoder Interface Requirements
tREQs
CLOCK
VID_REQ
AUD_REQ
DATA_REQ
VAD_DATA[7:0]
VID_STRB
AUD_STRB
DATA_STRB
tSTRBd
tSTRBw
tVADh
tVADs
PARAMETER
PARAMETER
MIN
TYP
MAX
UNIT
tVADs
VAD data setup time
30
-
-
ns
tVADh
VAD data hold time
30
-
-
ns
tSTRBd
STRB to clock delay time
-
-
18
ns
tSTRBw
STRB pulse width
30
-
-
ns
tREQs
REQ setup time
5
-
-
ns



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