ISPMACH4ACPLDFAMILY datasheet(10/62 Pages) LATTICE

Part #	ISPMACH4ACPLDFAMILY

Description	High Performance E 2 CMOS In-System Programmable Logic

PDF	62 Pages

Scroll/Zoom	100%

Manufacturer	LATTICE [Lattice Semiconductor]

Direct Link	http://www.latticesemi.com

Logo

10 / 62 page

ispMACH 4A Family

Macrocell

The macrocell consists of a storage element, routing resources, a clock multiplexer, and

initialization control. The macrocell has two fundamental modes: synchronous and

asynchronous (Figure 5). The mode chosen only affects clocking and initialization in the

macrocell.

In either mode, a combinatorial path can be used. For combinatorial logic, the synchronous

mode will generally be used, since it provides more product terms in the allocator.

SWAP

D/T/L

Power-Up

Reset

PAL-Block

Initialization

Product Terms

From Logic Allocator

Block CLK0

Block CLK1

Block CLK2

Block CLK3

To Output and Input

Switch Matrices

Common PAL-block resource

Individual macrocell resources

From

PAL-Clock

Generator

D/T/L

Power-Up

Reset

Individual

Initialization

Product Term

From Logic

Allocator

Block CLK0

Block CLK1

To Output and Input

Switch Matrices

Individual Clock

Product Term

From PAL-Block

Clock Generator

17466G-010

Figure 5. Macrocell

17466G-009

a. Synchronous mode

b. Asynchronous mode

ISPMACH4ACPLDFAMILY Datasheet(PDF) 10 Page - Lattice Semiconductor

ISPMACH4ACPLDFAMILY Datasheet(HTML) 10 Page - Lattice Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62

Datasheet Download

Link URL