ISPMACH4ACPLDFAMILY datasheet(19/62 Pages) LATTICE

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ispMACH 4A Family

PAL Block Clock Generation

Each ispMACH 4A device has four clock pins that can also be used as inputs. These pins drive

a clock generator in each PAL block (Figure 14). The clock generator provides four clock signals

that can be used anywhere in the PAL block. These four PAL block clock signals can consist of

a large number of combinations of the true and complement edges of the global clock signals.

Table 14 lists the possible combinations.

1. M4A(3,5)-32/32 and M4A(3,5)-64/32 have only two clock pins, GCLK0 and GCLK1. GCLK2 is tied to GCLK0, and GCLK3 is

tied to GCLK1.

Note:

1. Values in parentheses are for the M4A(3,5)-32/32 and M4A(3,5)-64/32.

This feature provides high ﬂexibility for partitioning state machines and dual-phase clocks. It

also allows latches to be driven with either polarity of latch enable, and in a master-slave

conﬁguration.

Table 14. PAL Block Clock Combinations1

Block CLK0

Block CLK1

Block CLK2

Block CLK3

GCLK0

GCLK1

GCLK0

GCLK1

GCLK0

GCLK2 (GCLK0)

GCLK3 (GCLK1)

GCLK2 (GCLK0)

GCLK3 (GCLK1)

GCLK2 (GCLK0)

GCLK0

GCLK1

GCLK2

GCLK3

Block CLK0

(GCLK0 or GCLK1)

Block CLK1

(GCLK1 or GCLK0)

Block CLK2

(GCLK2 or GCLK3)

Block CLK3

(GCLK3 or GCLK2)

17466G-004

Figure 14. PAL Block Clock Generator 1

ISPMACH4ACPLDFAMILY Datasheet(PDF) 19 Page - Lattice Semiconductor

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