TDC-GPX datasheet(27/54 Pages) AMSCO

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TDC-GPX

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the data to the Interface FIFO, which is 256 stages

deep. This is done with respect to automatic band-

width distribution. If a hit from one channel has been

processed, the neighbored channel gets highest prior-

ity for next operation. If there is no hit on the next, the

next sequential gets priority and so on. The maximum

rate for transfer into the Interface FIFO is 40 MHz. So

if there are hits on all channels equally distributed, the

maximum rate per channel is 10 MHz. If there are hits

on only one channel, this channel has 40 MHz maxi-

mum rate.

Finally a data multiplexer adds data from both Inter-

face FIFOs to the data bus. The data bus is 28 Bits

wide and capable of 40 MHz transfer rate. The data

bus can be switched to 16 Bit width writing

0x0000010 into address 14. A LOW at pin ‘Output

enable’ forces the bidirectional bus drivers to perma-

nent output state. This is helpful for fast data read out

routines.

Each Interface FIFO has an empty flag (EF) and a load-

level flag (LF). All flags are HIGH active. At low data

rates it is recommended to check the EF to see

whether there are data available for read out. It is not

allowed to read from an empty Interface FIFO. The LF

is helpful at high data rates. The load level threshold

can be set in ‘Fill’ in register 6 and is the same for

both FIFOs. As soon as the set number of data is avail-

able this can be read from the FIFO as a block without

the need of checking the EF.

Note: the load-level flags are not synchronized. The

load-level flag for a FIFO is valid only if it is not read

from this FIFO. Otherwise there might be spikes.

2.4 Data structure

The output data are integers with a BIN width defined

by the setting of the resolution adjust unit (1.6.1 Reso-

lution adjust),

hsdiv

216

BIN

refclkdiv

ref

Bits

27...26

Bits

25…18

Bit

Bits

16…0

Channel

code

Start#

= Start

number

Slope

Time interval data

Hit = Stop-Start

The time interval is calculated (externally) as:

If Start# is 0:

Time = 1 BIN(ps) * (Hit – StartOff1)

If Start# > 0:

Time = 1 BIN(ps) * (Hit – StartOff1 + Start01

+ (Start# - 1) * (StartTimer +1) * Tref

2.5 Reset

There are 3 ways of resetting the device:

Power-up reset: a low signal at pin PURESN

resets the whole chip.

Master-Reset: this command resets everything

except the configuration registers. It can be done

by software writing to register 4. When Master-

AluTrig in register 5 is set to ‘1’ it can be done

also by a HIGH at the Alutrigger input pin.

Partial-Reset: this command resets everything

except the configuration registers and the Inter-

face FIFOs. It can be done by software writing to

set to ‘1’ it can be done also by a HIGH at the

Alutrigger input pin.

After a Power-on reset and a Master reset it takes 40

ns before the Start and Stop inputs accept data.

After a Partial reset it takes 75 ns before the Start

and Stop inputs accept data.

2.6 MTimer

There is an internal timer available for internal use.

The main application will be setting a dedicated time

interval between 25ns and 204.7 µs after which the

interrupt flag is set. The period is set in ‘MTimer’,

8191 * Tref = 204.7 µs. The timer can be started by

a Stop and/or Start signal. This is set in ‘MTimerStart’

and ‘MTimerStop’, register 4. Setting Bit ‘TimerFlag’,

stops.

2.7 Interrupt Flag

The user can select on which event(s) the interrupt

flag is set.

The selection is done in register 12, Bits 13 to 25, by

unmasking the dedicated bits. They are combined by

an Or-Gate to the interrupt flag.

Selectable events are

Hit FIFOs 1, 2 …or/and 8 are full

Interface FIFOs 1 or/and 2 are full

PLL not locked

All Hit FIFOs empty

End of Mtimer

2.8 Error Flag

The user can select on which event(s) the error flag is

set.

The selection is done in register 11, Bits 16 to 26, by

unmasking the dedicated bits. They are combined by

an Or-Gate to the error flag.

Selectable events are

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