TDC-GPX datasheet(4/54 Pages) AMSCO

4 / 54 page

TDC-GPX

acam-messelectronic gmbh - Am Hasenbiel 27 - D-76297 Stutensee-Blankenloch - Germany - www.acam.de

1. Introduction

1.1 System overview

TQFP100

TFBGA120

I-Mode

8 channels with typ. 81 ps resolution

9 LVTTL inputs, optional 3 LVPECL

inputs

5.5 ns pulse-pair resolution with

32-fold multi-hit capability = 182 MHz

peak rate

Trigger to rising or falling edge

Measurement range 9,8 µs

, endless

measurement range by internal

retrigger of START

10 MHz continuous rate per channel

40 MHz continuous rate per chip

G-Mode

2 channels with 40 ps resolution

Differential LVPECL inputs, optional LVTTL

Measurement range 0 ns to 65 µs

5.5 ns pulse-pair resolution between edges of

equal slope with 32-fold multi-hit = 182 MHz peak

rate

Minimum pulse width 1.5 ns

Trigger to rising and falling edge

Optional Quiet Mode (no ALU operation and Data-

output during measurements)

20 MHz continuous rate per channel

40 MHz continuous rate per chip

R-Mode

2 channels with 27 ps resolution

Differential LVPECL inputs, optional LVTTL

Measurement range 0 µs up to

40 µs

5.5 ns pulse-pair resolution with 32-fold multi-hit

capability = 182 MHz peak rate

Trigger to rising or falling edge

Optional Quiet Mode (no ALU operation and Data-

output during measurements)

40 MHz continuous rate per channel

40 MHz continuous rate per chip

M-Mode

2 channels with 10 ps resolution

(70 ps peak-peak)

Differential LVPECL inputs

Measurement range 0 ns up to 10 µs

Single hit per Start and channel

Trigger to rising or falling edge

Quiet Mode (no ALU operation and Data-output

during measurements)

Max. 500 kHz continuous rate per channel

Max. 1 MHz continuous rate per chip

General

Start retrigger option (besides M-Mode)

Packages: TQFP100, TFBGA120

IO voltage 3.0 V – 3.6 V

Core voltage 2.3 V – 3.6 V regulated by resolution

adjust unit

Data bus: 28 Bit or 2 x 16 Bit asynchronous with

Chipselect, Readstrobe, Writestrobe

40 MHz continuous rate per chip

Address range: 4 Bit

DStart

TStart

DStop1 DStop2

TStop1 TStop2 TStop3 TStop4 TStop5 TStop6 TStop7 TStop8

LVPECL inputs

LVTTL inputs

Input Logic

Measurement Core

Hit FIFOs

Start

Logic

Post-processing

Interface FIFO1

Interface FIFO2

Data multiplexer

Read/Write logic

Configuration

registers

MTimer

Int and Error

flags

Data bus 28 or 2 x 16

WRN

RDN

CSN

ADR

OEN/

Reset

PLL

ErrFlag

40 MHz

ref

Phase

AluTrigger/

Reset

Power-on

reset

StartDis

StopDis

EF1

EF2

LF1

LF2

IntFlag

Master

reset

Partial

reset

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