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TDC-GPX Datasheet(PDF) 49 Page - ams AG

Part # TDC-GPX
Description  Ultra-high Performance 8 Channel Time- to-Digital Converter
PDF  54 Pages
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Manufacturer  AMSCO [ams AG]
Direct Link  http://www.ams.com
Logo AMSCO - ams AG

TDC-GPX Datasheet(HTML) 49 Page - ams AG

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TDC-GPX
acam-messelectronic gmbh - Am Hasenbiel 27 - D-76297 Stutensee-Blankenloch - Germany - www.acam.de
48
2. Apply Start and Stop signals with a short delay (e.g.
12ns)
3. Step down the interval and look at the output data.
They are getting smaller and smaller until you pass
the internal Start time stamp. The output data then
jumps to a very high value.
4. Take the time interval tcross (from your generator)
where this happens
5. Calculate StartOff1 = tcross / BIN and write this
value into register 5, StartOff1. In case you expect
negative values add an additional amount X to Star-
tOff1 and substract this value later on from your
output data
Internal Data Processing
The raw values of the stop events are stored in the Hit
FIFOs.
The following pipelined post-processing unit is respon-
sible for compression, Start selection and correct
Stop-Start subtraction. Subsequently a collection unit
transfers the data to the Interface FIFOs. Each channel
has its own interface FIFO. The maximum rate for
transfer into the Interface FIFO is 40 MHz.
Finally a data multiplexer adds data from both Inter-
face FIFOs to the data bus. The data bus is 28 Bits
wide and capable of 40 MHz transfer rate. The data
bus can be switched to 16 Bit width writing
0x0000010 into address 14. A LOW at pin ‘Output
enable’ forces the bidirectional bus drivers to perma-
nent output state. This is helpful for fast data read out
routines.
Each Interface FIFO has an empty flag (EF) and a load-
level flag (LF). All flags are HIGH active. At low data
rates it is recommended to check the EF to see
whether there are data available for read out. It is not
allowed to read from an empty Interface FIFO. The LF
is helpful at high data rates. The load level threshold
can be set in ‘Fill’ in register 6 and is the same for
both FIFOs. As soon as the set number of data is avail-
able this can be read from the FIFO as a block without
the need of checking the EF.
Note: the load-level flags are not synchronized. The
load-level flag for a FIFO is valid only if it is not read
from this FIFO. Otherwise there might be spikes.
Quiet Mode
In M-Mode it is mandatory to use the Quiet mode.
In Quiet Mode the post-processing and calculation
does not start automatically after each single event,
but after a dedicated trigger. The trigger can be given
externally by a rising slope at pin ALUTRIGGER or by
software setting a dedicated ALU-Trigger Bit.
The time needed from the start of the post-processing
until first data is available in the interface FIFO is typ.
900 ns.
5.4 Data structure and readout
The output results are integers with a LSB width de-
fined by the setting of the resolution adjust unit, di-
vided by MSet.
1
MSet
1
3
1
hsdiv
216
2
T
BIN
refclkdiv
ref
+
×
×
×
×
=
Bit 27 … 23
Bit 22...0
Not used
Edge-to-Start result of the ad-
dressed combined channel
The data can be read from address 8 for interface
FIFO1 and from address 9 for interface FIFO2.
5.5 Reset
There are 3 ways of resetting the device:
Power-up reset: a low signal at pin PURESN
resets the whole chip.
Master-Reset: this command resets everything
except the configuration registers. It can be done
by software writing to register 4. In non-quiet
mode MasterAluTrig in register 5 can be set to
‘1’. Then this command can be done also by a
HIGH at the Alutrigger input pin. In quiet mode
MasterOenTrig in register 5 can be set to ‘1’.
Then this command can be done also by a LOW at
the OEN input pin (only with OEN off).
Partial-Reset: this command resets everything
except the configuration registers and the Inter-
face FIFOs. It can be done by software writing to
register 4. In non-quiet mode Partial-AluTrig in
register 5 can be set to ‘1’. Then this command
can be done also by a HIGH at the Alutrigger in-
put pin. In quiet mode PartialOenTrig in register 5
can be set to ‘1’. Then this command can be done
also by a LOW at the OEN input pin (only with OEN
off).
After a Power-on reset or a Master reset it takes 40
ns before the Start and Stop inputs accept data.
After a Partial reset it takes 75 ns before the Start
and Stop inputs accept data.
Member of the ams Group



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