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TMP320C2811PBKA Datasheet(PDF) 138 Page - Texas Instruments

Part # TMP320C2811PBKA
Description  TMS320R2811, TMS320R2812 Digital Signal Processors
PDF  147 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TMP320C2811PBKA Datasheet(HTML) 138 Page - Texas Instruments

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Electrical Specifications
138
June 2004
SPRS257
6.30.2 McBSP as SPI Master or Slave Timing
Table 6−45. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0)
NO
MASTER
SLAVE
UNIT
NO.
MIN
MAX
MIN
MAX
UNIT
M30
tsu(DRV-CKXL)
Setup time, DR valid before CLKX low
P-10
8P-10
ns
M31
th(CKXL-DRV)
Hold time, DR valid after CLKX low
P-10
8P-10
ns
M32
tsu(BFXL-CKXH)
Setup time, FSX low before CLKX high
8P+10
ns
M33
tc(CKX)
Cycle time, CLKX
2P
16P
ns
Table 6−46. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0)†
NO
PARAMETER
MASTER
SLAVE
UNIT
NO.
PARAMETER
MIN
MAX
MIN
MAX
UNIT
M24
th(CKXL-FXL)
Hold time, FSX low after CLKX low
2P
ns
M25
td(FXL-CKXH)
Delay time, FSX low to CLKX high
P
ns
M28
tdis(FXH-DXHZ)
Disable time, DX high impedance following
last data bit from FSX high
6
6P + 6
ns
M29
td(FXL-DXV)
Delay time, FSX low to DX valid
6
4P + 6
ns
† 2P = 1/CLKG
For all SPI slave modes, CLKX has to be minimum 8 CLKG cycles. Also CLKG should be LSPCLK/2 by setting CLKSM = CLKGDV = 1. With
maximum LSPCLK speed of 75 MHz, CLKX maximum frequency will be LSPCLK/16 , that is 4.5 MHz and P =13.3 ns.
Bit 0
Bit(n-1)
(n-2)
(n-3)
(n-4)
Bit 0
Bit(n-1)
(n-2)
(n-3)
(n-4)
CLKX
FSX
DX
M30
M31
DR
M28
M24
M29
M25
LSB
MSB
M32
M33
Figure 6−40. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0



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