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TMP320C2811PBKA Datasheet(PDF) 140 Page - Texas Instruments

Part # TMP320C2811PBKA
Description  TMS320R2811, TMS320R2812 Digital Signal Processors
PDF  147 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TMP320C2811PBKA Datasheet(HTML) 140 Page - Texas Instruments

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Electrical Specifications
140
June 2004
SPRS257
Table 6−49. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1)†
NO
MASTER
SLAVE
UNIT
NO.
MIN
MAX
MIN
MAX
UNIT
M49
tsu(DRV-CKXH)
Setup time, DR valid before CLKX high
P-10
8P-10
ns
M50
th(CKXH-DRV)
Hold time, DR valid after CLKX high
P-10
8P-10
ns
M51
tsu(FXL-CKXL)
Setup time, FSX low before CLKX low
8P+10
ns
M52
tc(CKX)
Cycle time, CLKX
2P
16P
ns
Table 6−50. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1)†
NO
PARAMETER
MASTER
SLAVE
UNIT
NO.
PARAMETER
MIN
MAX
MIN
MAX
UNIT
M43
th(CKXH-FXL)
Hold time, FSX low after CLKX high
2P
ns
M44
td(FXL-CKXL)
Delay time, FSX low to CLKX low
P
ns
M47
tdis(FXH-DXHZ)
Disable time, DX high impedance following last data bit
from FSX high
6
6P + 6
ns
M48
td(FXL-DXV)
Delay time, FSX low to DX valid
6
4P + 6
ns
† 2P = 1/CLKG
For all SPI slave modes, CLKX has to be minimum 8 CLKG cycles. Also CLKG should be LSPCLK/2 by setting CLKSM = CLKGDV = 1. With
maximum LSPCLK speed of 75 MHz, CLKX maximum frequency will be LSPCLK/16 , that is 4.5 MHz and P =13.3 ns.
M51
M50
M47
Bit 0
Bit(n-1)
(n-2)
(n-3)
(n-4)
Bit 0
Bit(n-1)
(n-2)
(n-3)
(n-4)
CLKX
FSX
DX
DR
M44
M48
M49
M43
LSB
MSB
M52
Figure 6−42. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1



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