SCANSTA111MTSLASHNOPB datasheet(17/38 Pages) TI1

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SCANSTA111

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SNLS060K – AUGUST 2001 – REVISED APRIL 2013

MODE REGISTER0

Mode Register0 is an 8-bit data register used primarily to configure the Local Scan Port Network. Mode Register0

is initialized to 00000001 binary upon entering the Test-Logic-Reset state. Bits 0, 1, 2, and 4 are used for scan

chain configuration as described in Table 6. When the UNPARK instruction is executed, the scan chain

configuration is as shown in Table 6 below. When all LSPs are parked, the scan chain configuration is TDIB →

'STA111-register

→ TDOB. Bit 3 is used for TCKn configuration, see Table 7.

Table 6. Mode Register Control of LSPN(1)

Mode Register(s)

Scan Chain Configuration (if unparked)

MR0: X000X000

TDIB → Register → TDOB

MR0: X000X001

TDIB → Register → LSP0 → PAD → TDOB

MR0: X000X010

TDIB → Register → LSP1 → PAD → TDOB

MR0: X000X011

TDIB → Register → LSP0 → PAD → LSP1 → PAD → TDOB

MR0: X000X100

TDIB → Register → LSP2 → PAD → TDOB

MR0: X000X101

TDIB → Register → LSP0 → PAD → LSP2 → PAD → TDOB

MR0: X000X110

TDIB → Register → LSP1 → PAD → LSP2 → PAD → TDOB

MR0: X000X111

TDIB → Register → LSP0 → PAD → LSP1 → PAD → LSP2 → PAD → TDOB

MR0: X010X000

TDIB → Register → LSP3 → PAD → TDOB

MR0: X010X001

TDIB → Register → LSP0 → PAD → LSP3 → PAD → TDOB

MR0: X010X010

TDIB → Register → LSP1 → PAD → LSP3 → PAD → TDOB

MR0: X010X011

TDIB → Register → LSP0 → PAD → LSP1 → PAD → LSP5 → PAD → TDOB

MR0: X010X100

TDIB → Register → LSP2 → PAD → LSP3 → PAD → TDOB

...

MR0: X110X111

TDIB → Register → LSP0 → PAD → LSP1 → PAD → LSP2 → PAD → LSP3 → PAD → LSP4 → PAD → TDOB

MR0: X000X000MR1:

TDIB → Register → LSP5 → PAD → TDOB

XXXXX001 (2)

MR0: X000X001MR1:

TDIB → Register → LSP0 → PAD → LSP5 → PAD → TDOB

XXXXX001 (2)

MR0: X000X010MR1:

TDIB → Register → LSP1 → PAD → LSP5 → PAD → TDOB

XXXXX001 (2)

...

MR0: X110X111MR1:

TDIB → Register → LSP0 → PAD →→ LSP1 → PAD → LSP2 → PAD → LSP3 → PAD → LSP4 → PAD → LSP5 →

XXXXX001 (2)

PAD

→ TDOB

MR0: X000X000MR1:

TDIB → Register → LSP6 → PAD → TDOB

XXXXX010 (2)

...

MR0: X110X111MR1:

TDIB → Register → LSP0 → PAD → LSP1 → PAD → LSP2 → PAD → LSP3 → PAD → LSP4 → PAD → LSP5 →

XXXXX111 (2)

PAD

→ LSP6 → PAD → LSP7 → PAD → TDOB

MR0:

TDIB → Register → TDOB (Loopback)

XXX1XXXXMR1:

XXXXXXXX (2)

(1)

In a device with 8 LSPs there are 28 possible LSPN configurations: No LSPs, each individual LSP, combinations of 2 to 7 LSPs, and all

8 LSPs.

(2)

Mode Register1 is only available in the HDL version (up to eight LSPs). The Silicon version has three LSPs and uses Mode Register0 for

LSP selection.

Table 7. Test Clock Configuration

Bit 3

LSP n

TCK n

Parked

Stopped

Parked

Free-running

Unparked

Free-running

Unparked

Free-running

Parked-TLR

Stopped after 512 clock pulses

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