SCANSTA111

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SNLS060K – AUGUST 2001 – REVISED APRIL 2013

PIN DESCRIPTIONS (continued)

No.

Pin Name

Pins

I/O

Description

3

O

LOCAL ANALOG TEST BUS ENABLE: These analog pins serve as enable signals for analog

busses supporting the IEEE 1149.4 Mixed-Signal Test Bus standard , or for backplane physical

layer changes (therefore; TTL to LVDS). These outputs have 12mA of drive current.

3

O

LOCAL TRI-STATE NOTIFICATION OUTPUTS: This signal is high when the local scan ports are

TRI-STATEd . These pins are used for backplane physical layer changes (i.e.; TTL to LVDS). These

outputs have 12mA of drive current.

TEST ENABLE

1

I

operation.

APPLICATION OVERVIEW

ADDRESSING SCHEME - The SCANSTA111 architecture extends the functionality of the IEEE 1149.1 Standard

by supplementing that protocol with an addressing scheme which allows a test controller to communicate with

specific 'STA111s within a network of 'STA111s. That network can include both multi-drop and hierarchical

connectivity. In effect, the 'STA111 architecture allows a test controller to dynamically select specific portions of

such a network for participation in scan operations. This allows a complex system to be partitioned into smaller

blocks for testing purposes. The 'STA111 provides two levels of test-network partitioning capability. First, a test

controller can select individual 'STA111s, specific sets of 'STA111s (multi-cast groups), or all 'STA111s

(broadcast). This 'STA111-selection process is supported by a Level-1 communication protocol. Second, within

each selected 'STA111, a test controller can select one or more of the chip's three local scan-ports. That is,

individual local ports can be selected for inclusion in the (single) scan-chain which a 'STA111 presents to the test

controller. This mechanism allows a controller to select specific terminal scan-chains within the overall scan

network. The port-selection process is supported by a Level-2 protocol.

HIERARCHICAL SUPPORT - Multiple SCANSTA111's can be used to assemble a hierarchical boundary-scan

tree. In such a configuration, the system tester can configure the local ports of a set of 'STA111s so as to

connect a specific set of local scan-chains to the active scan chain. Using this capability, the tester can

selectively communicate with specific portions of a target system. The tester's scan port is connected to the

backplane scan port of a root layer of 'STA111s, each of which can be selected using multi-drop addressing. A

second tier of 'STA111s can be connected to this root layer, by connecting a local port (LSP) of a root-layer

'STA111 to the backplane port of a second-tier 'STA111. This process can be continued to construct a multi-level

scan hierarchy. 'STA111 local ports which are not cascaded into higher-level 'STA111s can be thought of as the

terminal leaves of a scan tree. The test master can select one or more target leaves by selecting and configuring

the local ports of an appropriate set of 'STA111s in the test tree.

Check with your ATPG tool vendor to ensure support of this feature.

STATE MACHINES

The 'STA111 is IEEE 1149.1-compatible, in that it supports all required 1149.1 operations. In addition, it supports

a higher level of protocol, (Level 1), that extends the IEEE 1149.1 Std. to a multi-drop environment.

In multi-drop scan systems, a scan tester can select individual 'STA111s for participation in upcoming scan

operations. STA111 selection is accomplished by simultaneously scanning a device address out to multiple

'STA111s. Through an on-chip address matching process, only those 'STA111s whose statically-assigned

address matches the scanned-out address become selected to receive further instructions from the scan tester.

SCANSTA111 selection is done using a Level-1 protocol, while follow-on instructions are sent to selected

'STA111s by using a Level-2 protocol.

Copyright © 2001–2013, Texas Instruments Incorporated

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