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PC33991DH/R2 Datasheet(PDF) 25 Page - Motorola, Inc |
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PC33991DH/R2 Datasheet(HTML) 25 Page - Motorola, Inc |
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25 / 36 page  MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA 33991 25 Internal Clock Calibration Timing related functions on the 33991 device (e.g., pointer velocities, acceleration and Return To Zero Pointer speeds) depend upon a precise, consistent time reference to control the pointer accurately and reliably. Generating accurate time references on an Integrated Circuit can be accomplished; however, they tend to be costly due to the large amount of die area required for trim pads and the associated trim procedure. One possibility to reduce cost is an externally generated clock signal. An external generated clock requires a dedicated pin on the device and on the controller. Another inexpensive approach would be to require the use of an additional crystal or resonator. The internal clock in the 33991 is temperature independent and area efficient; however, it can vary by as much as + 70 percent to - 35 percent due to process variation. Using the existing SPI inputs and the precision timing reference already available to the controller, the 33991allows clock calibration to within ± 10 percent. Calibrating the internal 1 MHz clock is initiated by writing a logic [1] to PECR bit D3. See Figure 7. The 8 µs calibration pulse is provided by the controller. It is ideally results in an internal 33991 clock speed of 1 MHz. The pulse is sent on the CS pin immediately after the SPI word is launched. No other SPI lines must be toggled. At the moment the CS pin transitions from logic [1] to [0], an internal 7-bit counter counts the number of cycles of an internal, non-calibrated, and temperature independent, 8 MHz clock. The counter stops when the CS pin transitions from logic [0] to logic [1]. The value in the counter represents the number of cycles of the 8 MHz clock occurring in the 8 µs window; it should range from 32 to 119. An offset is added to this number to help center or skew the calibrated result to generate a desired maximum or nominal frequency. The modified counter value is truncated by four bits, generating the calibration divisor, ranging from four to 15. The 8 MHz clock is divided by the calibration divisor, resulting in a calibrated 1 MHz clock. If the calibration divisor lies outside the range of four to 15, then the 33991 device flags the ST7 bit, indicating the 48 447 2256.30 120 280 3587.05 192 221 4543.45 49 442 2280.11 121 279 3602.07 193 220 4555.32 50 437 2303.67 122 278 3617.03 194 220 4567.15 51 433 2326.99 123 277 3631.93 195 219 4578.96 52 429 2350.09 124 275 3646.77 196 219 4590.74 53 425 2372.95 125 274 3661.54 197 218 4602.49 54 420 2395.60 126 273 3676.26 198 218 4614.21 55 417 2418.04 127 272 3690.92 199 217 4625.89 56 413 2440.27 128 271 3705.52 200 216 4637.55 57 409 2462.30 129 270 3720.07 201 216 4649.18 58 405 2484.13 130 269 3734.56 202 215 4660.78 59 402 2505.77 131 268 3748.99 203 215 4672.36 60 398 2527.23 132 267 3763.36 204 214 4683.90 61 395 2548.51 133 266 3777.68 205 214 4695.41 62 392 2569.61 134 265 3791.95 206 213 4706.90 63 389 2590.54 135 264 3806.17 207 213 4718.36 64 385 2611.30 136 263 3820.33 208 212 4729.79 65 382 2631.90 137 262 3834.44 209 212 4741.19 66 379 2652.34 138 261 3848.49 210 211 4752.57 67 376 2672.62 139 260 3862.50 211 211 4763.92 68 374 2692.75 140 259 3876.45 212 210 4775.24 69 371 2712.73 141 258 3890.36 213 210 4786.53 70 368 2732.56 142 257 3904.22 214 209 4797.80 71 366 2752.25 143 256 3918.02 215 209 4800.00 Table 14. Velocity Ramp Velocity Position Time Between Steps ( µs) Velocity ( µSteps/s) Velocity Position Time Between Steps ( µs) Velocity ( µSteps/s) Velocity Position Time Between Steps ( µs) Velocity ( µSteps/s) Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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