STLED524 datasheet(25/72 Pages) STMICROELECTRONICS

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STLED524

Detailed description

BLK[2:0] - blanking time duration

000: 2 clock periods

001: 4 clock periods

010: 6 clock periods

011: 8 clock periods

100: 10 clock periods

101: 12 clock periods

110: 14 clock periods

111: 16 clock periods

These bits can be read or written in any configuration, these registers should be changed

when EN=0. See Section 4.2.1 for details.

4.5.7

Boost control register

This register is described in Section 4.1.

4.5.8

Display visual control register

This register enables/disables the driver visual features.

PWMEN = 0, PWM duty cycle is fixed to maximum available

PWMEN = 1, PWM duty cycle can be customized by PWM control register

SCRLEN = 0, scrolling is disabled

SCRLEN = 1, scrolling is enabled

SLPEN = 0, slope operation is disabled

SLPEN = 1, slope operation is enabled

WAITEN = 0, wait time at the end of scroll operation is disabled

WAITEN = 1, wait time at the end of scroll operation is enabled

BRCEN = 0, insertion of blank rows/columns during scroll operation is disabled

BRCEN = 1, insertion of blank rows/columns during scroll operation is enabled

DISPSIZE = 0, full number of columns is used to display content of patterns 1 and 2

DISPSIZE = 1, content of columns 20-23 is always linked to pattern 1 regardless of the

value of DISP bits. If content of pattern 2 is displayed, then columns 0-19 are visible. The

rest is "hidden behind" in the columns 20-23 that display content of pattern 1 permanently.

Table 26. Display visual control register

Display visual

control

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Add = 20h

BRCEN WAITEN

SLPEN

SCRLEN

PWMEN

DISPSIZE

Default

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