TMS320DM814X datasheet(10/377 Pages) TI1

10 / 377 page

TMS320DM8148, TMS320DM8147

SPRS647E – MARCH 2011 – REVISED DECEMBER 2013

www.ti.com

SEE

ADDITIONS/MODIFICATIONS/DELETIONS

Section 7.4.1.1, Using the Internal Oscillators:

Table 7-11, Requirements for Crystal Circuit on the Device Oscillator (DEVOSC):

•

Added three conditions and the MAX values to the Crystal Frequency Stability PARAMETER

Table 7-15, Timing Requirements for DEVOSC_MXI/DEV_CLKIN

•

Added three conditions and the MAX values to the Frequency Stability PARAMETER

Section 7.4.3, AUD_CLKINx Input Clocks:

•

Added section [New]

Section 7.4

Clocking

Section 7.4.4, CLKIN32 Input Clock:

•

Added "/8" to the TIMER1/2/3/4/5/6/7 bullet

Section 7.4.7, Input/Output Clocks Electrical Data/Timing:

•

Added Table 7-17, Timing Requirements for AUD_CLKINx [New]

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Added Figure 7-14, AUD_CLKINx Timing [New]

Section 7.4.8, PLLs:

•

Deleted PLL Electrical Data/Timing subsection

Table 7-26, Maximum SYSCLK Clock Frequencies:

Section 7.4.9

SYSCLKs

•

Added footnote, "The maximum frequencies listed..."

Table 7-27, Maximum Module Clock Frequencies:

•

Updated/Changed Media Controller CLOCK SOURCES from "PLL_MEDIACTL" to

Section 7.4.10

"PLL_MEDIACTL/2"

Module Clocks

•

Updated/Changed Media Controller MAX FREQUENCY OPP100 (MHz) value from "400" to "200"

•

Added footnote, "The maximum frequencies listed..."

Section 8.4.1, EDMA Channel Synchronization Events:

•

Updated/Changed paragraphs

Section 8.4

Section 8.4.2, EDMA Peripheral Register Descriptions:

EDMA

•

Added Table 8-5, EDMA Channel Controller (EDMA TPCC) Control Registers

•

Added Table 8-6, EDMA Transfer Controller (EDMA TPTC) Control Registers

Table 8-8, JTAG ID Register Table:

Section 8.5.3

IEEE 1149.1 JTAG

•

Added silicon-revision specific information to the VARIANT bit field

Section 8.6.2.3

EMAC RGMII Electrical

•

Updated/Changed all instances of "at DSP" to "at device"

Data/Timing

Table 8-42, Timing Requirements for HDVPSS Input:

Section 8.10.1

HDVPSS Electrical

•

Deleted NO. 7, tt(CLK), Transition time, VIN[x]A_CLK (10%-90%)

Data/Timing

•

Deleted NO. 7, tt(CLK), Transition time, VIN[x]B_CLK (10%-90%)

Table 8-53, Switching Characteristics Over Recommended Operating Conditions for DDR2/DDR3

Section 8.13.4,

Memory Controller:

DDR2/DDR3 Memory

•

Updated/Changed NO. 1, tc(DDR_CLK) , Cycle time, DDR[x]_CLK, DDR2/DDR3 mode to DDR2

Controller Electrical

mode

Data/Timing

•

Added additional row to NO.1, tc(DDR_CLK), Cycle time, DDR[x]_CLK: DDR3 mode

Section 8.13.4.1.1.1, DDR2 Interface Schematic:

•

Updated/Changed the sentence from, "... pins by pulling the non-inverted DQS pin..." to "...

Section 8.13.4.1

DDR[x]_DQS[n] pins to the corresponding..."

DDR2 Routing

Specifications

•

Updated/Changed a sentence from, "... inverted DQS pin..." to "... DDR[x]_DQS[n] pins..."

•

Added sentence, "The DVDD_DDR[x] and VREFSSTL_DDR[x] power..."

Section 8.13.4.1.2

Table 8-63, CK and ADDR_CTRL Routing Specification:

DDR2 CK and

•

Updated/Changed the "Series terminator,...the DSP" footnote to "Series terminator,..the processor"

ADDR_CTRL Routing

Section 8.13.4.2.4, DDR3 Interface Schematic:

•

Combined 16-Bit and 32-Bit DDR3 Interface subsections

Section 8.13.4.2

DDR3 Routing

•

Deleted repeated figure references

Specifications

•

Deleted the sentence, "and the unused DQS......pulled to ground via 1-k

Ω resistors."

•

Added sentence, "The DVDD_DDR[x] and VREFSSTL_DDR[x]..."

Contents

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