SPC56ECxx datasheet(89/123 Pages) STMICROELECTRONICS

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SPC564Bxx-SPC56ECxx

Electrical Characteristics

122

This relation can again be simplified considering CS as an additional worst condition. In

reality, transient is faster, but the A/D converter circuitry has been designed to be robust

also in very worst case: the sampling time Ts is always much longer than the internal time

constant.

Equation 6

The charge of CP1 and CP2 is redistributed on CS,determining a new value of the voltage

VA1 on the capacitance according to the following equation

Equation 7

A second charge transfer involves also CF (that is typically bigger than the on-chip

capacitance) through the resistance RL: again considering the worst case in which CP2 and

CS were in parallel to CP1 (since the time constant in reality would be faster), the time

constant is:

Equation 8

In this case, the time constant depends on the external circuit: in particular imposing that the

transient is completed well before the end of sampling time TS, a constraints on RL sizing is

obtained:

Equation 9

Of course, RL shall be sized also according to the current limitation constraints, in

combination with RS (source impedance) and RF (filter resistance). Being CF definitively

bigger than CP1, CP2 and CS, then the final voltage VA2 (at the end of the charge transfer

transient) will be much higher than VA1. The following equation must be respected (charge

balance assuming now CS already charged at VA1):

Equation 10

The two transients above are not influenced by the voltage source that, due to the presence

of the RFCF filter, is not able to provide the extra charge to compensate the voltage drop on

CS with respect to the ideal source VA; the time constant RFCF of the filter is very high with

respect to the sampling time (TS). The filter is typically designed to act as anti-aliasing

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