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R5F56519FDFP Datasheet(PDF) 103 Page - Renesas Technology Corp |
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R5F56519FDFP Datasheet(HTML) 103 Page - Renesas Technology Corp |
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103 / 190 page  R01DS0276EJ0100 Rev.1.00 Page 103 of 190 Aug 24, 2016 RX65N Group, RX651 Group 4. I/O Registers 000C 0120h ETHER C0 PHY Interface Register PIR 32 32 13, 14 PCLKA 1 to 7 ICLK ETHER C 000C 0128h ETHER C0 PHY Status Register PSR 32 32 13, 14 PCLKA 1 to 7 ICLK ETHER C 000C 0140h ETHER C0 Random Number Generation Counter Limit Setting Register RDMLR 32 32 13, 14 PCLKA 1 to 7 ICLK ETHER C 000C 0150h ETHER C0 Interpacket Gap Register IPGR 32 32 13, 14 PCLKA 1 to 7 ICLK ETHER C 000C 0154h ETHER C0 Automatic PAUSE Frame Register APR 32 32 13, 14 PCLKA 1 to 7 ICLK ETHER C 000C 0158h ETHER C0 Manual PAUSE Frame Register MPR 32 32 13, 14 PCLKA 1 to 7 ICLK ETHER C 000C 0160h ETHER C0 Received PAUSE Frame Counter RFCF 32 32 13, 14 PCLKA 1 to 7 ICLK ETHER C 000C 0164h ETHER C0 PAUSE Frame Retransmit Count Setting Register TPAUSER 32 32 13, 14 PCLKA 1 to 7 ICLK ETHER C 000C 0168h ETHER C0 PAUSE Frame Retransmit Counter TPAUSECR 32 32 13, 14 PCLKA 1 to 7 ICLK ETHER C 000C 016Ch ETHER C0 Broadcast Frame Receive Count Setting Register BCFRR 32 32 13, 14 PCLKA 1 to 7 ICLK ETHER C 000C 01C0h ETHER C0 MAC Address Upper Bit Register MAHR 32 32 13, 14 PCLKA 1 to 7 ICLK ETHER C 000C 01C8h ETHER C0 MAC Address Lower Bit Register MALR 32 32 13, 14 PCLKA 1 to 7 ICLK ETHER C 000C 01D0h ETHER C0 Transmit Retry Over Counter Register TROCR 32 32 13, 14 PCLKA 1 to 7 ICLK ETHER C 000C 01D4h ETHER C0 Late Collision Detect Counter Register CDCR 32 32 13, 14 PCLKA 1 to 7 ICLK ETHER C 000C 01D8h ETHER C0 Lost Carrier Counter Register LCCR 32 32 13, 14 PCLKA 1 to 7 ICLK ETHER C 000C 01DCh ETHER C0 Carrier Not Detect Counter Register CNDCR 32 32 13, 14 PCLKA 1 to 7 ICLK ETHER C 000C 01E4h ETHER C0 CRC Error Frame Receive Counter Register CEFCR 32 32 13, 14 PCLKA 1 to 7 ICLK ETHER C 000C 01E8h ETHER C0 Frame Receive Error Counter Register FRECR 32 32 13, 14 PCLKA 1 to 7 ICLK ETHER C 000C 01ECh ETHER C0 Too-Short Frame Receive Counter Register TSFRCR 32 32 13, 14 PCLKA 1 to 7 ICLK ETHER C 000C 01F0h ETHER C0 Too-Long Frame Receive Counter Register TLFRCR 32 32 13, 14 PCLKA 1 to 7 ICLK ETHER C 000C 01F4h ETHER C0 Received Alignment Error Frame Counter Register RFCR 32 32 13, 14 PCLKA 1 to 7 ICLK ETHER C 000C 01F8h ETHER C0 Multicast Address Frame Receive Counter Register MAFCR 32 32 13, 14 PCLKA 1 to 7 ICLK ETHER C 000C 1200h MTU3 Timer Control Register TCR 8 8 4, 5 PCLKA 1, 2 ICLK MTU3a 000C 1201h MTU4 Timer Control Register TCR 8 8 4, 5 PCLKA 1, 2 ICLK MTU3a 000C 1202h MTU3 Timer Mode Register 1 TMDR1 8 8 4, 5 PCLKA 1, 2 ICLK MTU3a 000C 1203h MTU4 Timer Mode Register 1 TMDR1 8 8 4, 5 PCLKA 1, 2 ICLK MTU3a 000C 1204h MTU3 Timer I/O Control Register H TIORH 8 8 4, 5 PCLKA 1, 2 ICLK MTU3a 000C 1205h MTU3 Timer I/O Control Register L TIORL 8 8 4, 5 PCLKA 1, 2 ICLK MTU3a 000C 1206h MTU4 Timer I/O Control Register H TIORH 8 8 4, 5 PCLKA 1, 2 ICLK MTU3a 000C 1207h MTU4 Timer I/O Control Register L TIORL 8 8 4, 5 PCLKA 1, 2 ICLK MTU3a 000C 1208h MTU3 Timer Interrupt Enable Register TIER 8 8 4, 5 PCLKA 1, 2 ICLK MTU3a 000C 1209h MTU4 Timer Interrupt Enable Register TIER 8 8 4, 5 PCLKA 1, 2 ICLK MTU3a 000C 120Ah MTU Timer Output Master Enable Register A TOERA 8 8 4, 5 PCLKA 1, 2 ICLK MTU3a 000C 120Dh MTU Timer Gate Control Register A TGCRA 8 8 4, 5 PCLKA 1, 2 ICLK MTU3a 000C 120Eh MTU Timer Output Control Register 1A TOCR1A 8 8 4, 5 PCLKA 1, 2 ICLK MTU3a 000C 120Fh MTU Timer Output Control Register 2A TOCR2A 8 8 4, 5 PCLKA 1, 2 ICLK MTU3a 000C 1210h MTU3 Timer Counter TCNT 16 16 4, 5 PCLKA 1, 2 ICLK MTU3a Table 4.1 List of I/O Registers (Address Order) (49 / 56) Address Module Symbol Register Name Register Symbol Number of Bits Access Size Number of Access Cycles Related Function ICLK PCLK ICLK PCLK |
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