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R5F56519FDFP Datasheet(PDF) 159 Page - Renesas Technology Corp |
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R5F56519FDFP Datasheet(HTML) 159 Page - Renesas Technology Corp |
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159 / 190 page  R01DS0276EJ0100 Rev.1.00 Page 159 of 190 Aug 24, 2016 RX65N Group, RX651 Group 5. Electrical Characteristics Note: tIICcyc: RIIC internal reference clock (IIC) cycle Note 1. The value within parentheses is applicable when the value of the ICMR3.NF[1:0] bits is 11b while the digital filter is enabled by the setting ICFER.NFE = 1. Note 2. Cb is the total capacitance of the bus lines. Table 5.36 RIIC Timing (1) Conditions: VCC = AVCC0 = AVCC1 = VCC_USB = VBATT = 2.7 to 3.6 V, 2.7 ≤ VREFH0 ≤ AVCC0, VSS = AVSS0 = AVSS1 = VREFL0 = VSS_USB = 0 V, PCLKA = 8 to 120 MHz, PCLKB = 8 to 60 MHz, Ta = Topr, High-drive output is selected by the driving ability control register. Item Symbol Min.*1, *2 Max. Unit Test Conditions RIIC (Standard-mode, SMBus) ICFER.FMPE = 0 SCL input cycle time tSCL 6(12) × tIICcyc + 1300 — ns Figure 5.54 SCL input high pulse width tSCLH 3(6) × tIICcyc + 300 — ns SCL input low pulse width tSCLL 3(6) × tIICcyc + 300 — ns SCL, SDA input rise time tSr —1000 ns SCL, SDA input fall time tSf —300 ns SCL, SDA input spike pulse removal time tSP 0 1(4) × tIICcyc ns SDA input bus free time tBUF 3(6) × tIICcyc + 300 — ns Start condition input hold time tSTAH tIICcyc + 300 — ns Restart condition input setup time tSTAS 1000 — ns Stop condition input setup time tSTOS 1000 — ns Data input setup time tSDAS tIICcyc + 50 — ns Data input hold time tSDAH 0— ns SCL, SDA capacitive load Cb — 400 pF RIIC (Fast-mode) ICFER.FMPE = 0 SCL input cycle time tSCL 6(12) × tIICcyc + 600 — ns SCL input high pulse width tSCLH 3(6) × tIICcyc + 300 — ns SCL input low pulse width tSCLL 3(6) × tIICcyc + 300 — ns SCL, SDA input rise time tSr 20 × (External pull-up voltage/5.5V) 300 ns SCL, SDA input fall time tSf 20 × (External pull-up voltage/5.5V) 300 ns SCL, SDA input spike pulse removal time tSP 0 1(4) × tIICcyc ns SDA input bus free time tBUF 3(6) × tIICcyc + 300 — ns Start condition input hold time tSTAH tIICcyc + 300 — ns Restart condition input setup time tSTAS 300 — ns Stop condition input setup time tSTOS 300 — ns Data input setup time tSDAS tIICcyc + 50 — ns Data input hold time tSDAH 0— ns SCL, SDA capacitive load Cb — 400 pF |
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