MPC7450EC datasheet(37/52 Pages) MOTOROLA

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MPC7450 RISC Microprocessor Hardware Speciﬁcations

System Design Information

The MPC7450 generates the clock for the external L3 synchronous data SRAMs by dividing the core clock

frequency of the MPC7450. The core-to-L3 frequency divisor for the L3 PLL is selected through the

L3_CLK bits of the L3CR register. Generally, the divisor must be chosen according to the frequency

supported by the external RAMs, the frequency of the MPC7450 core, and timing analysis of the circuit

board routing. Table 17 shows various example L3 clock frequencies that can be obtained for a given set of

core frequencies.

0111

300

(600)

450

(900)

600

(1200)

675

(1350)

747

(1494)

1010

10x

333

(666)

500

(1000)

667

(1333)

750

(1500)

1001

11x

366

(733)

550

(1100)

733

(1466)

1011

12x

400

(800

600

(1200)

0101

13x

433

(866)

650

(1300)

1100

14x

466

(933)

700

(1400)

0001

15x

500

(1000)

750

(1500)

1101

16x

533

(1066)

0011

PLL off/bypass

PLL off, SYSCLK clocks core circuitry directly

1111

PLL off

PLL off, no core clocking occurs

Notes:

PLL_CFG[0:3] settings not listed are reserved.

The sample bus-to-core frequencies shown are for reference only. Some PLL conﬁgurations may select bus, core,

or VCO frequencies which are not useful, not supported, or not tested for by the MPC7450; see Section 1.5.2.1,

“Clock AC Speciﬁcations,” for valid SYSCLK, core, and VCO frequencies.

In PLL-bypass mode, the SYSCLK input signal clocks the internal processor directly and the PLL is disabled.

However, the bus interface unit requires a 2x clock to function. Therefore, an additional signal, EXT_QUAL, must

be driven at one-half the frequency of SYSCLK and offset in phase to meet the required input setup tIVKH and hold

time tIXKH (see Table 9). The result will be that the processor bus frequency will be one-half SYSCLK while the

internal processor is clocked at SYSCLK frequency. This mode is intended for factory use and emulator tool use

only.

Note: The AC timing speciﬁcations given in this document do not apply in PLL-bypass mode.

In PLL-off mode, no clocking occurs inside the MPC7450 regardless of the SYSCLK input.

Table 17. Sample Core-to-L3 Frequencies

Core Frequency (MHz)

÷2

÷2.5

÷3

÷3.5

÷4

÷5

÷6

500

250

200

167

143

125

100

533

266

213

178

152

133

107

Table 16. MPC7450 Microprocessor PLL Conﬁguration Example for 600 MHz Parts (continued)

PLL_EXT

PLL_CFG

[0:3]

Example Bus-to-Core Frequency in MHz (VCO Frequency in MHz)

Bus-to-

Core

Multiplier

Core-to-

VCO

Multiplier

Bus

33.3 MHz

Bus

50 MHz

Bus

66.6 MHz

Bus

75 MHz

Bus

83 MHz

Bus

100 MHz

Bus

133 MHz

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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